Page 1
Philips Semiconductors Product specification
Octal D-type transparent latch (3-State)
FEA TURES
•74ABT573A is flow-through pinout version of 74ABT373
•Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•3-State output buffers
•Common output enable
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•Power-up 3-State
•Power-up reset
DESCRIPTION
The 74ABT573A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
QUICK REFERENCE DAT A
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
Dn to Qn
CL = 50pF; VCC = 5V
Input capacitance VI = 0V or V
Output capacitance Outputs disabled; VO = 0V or V
Total supply current Outputs disabled; VCC =5.5V 100 µA
74ABT573A
The 74ABT573A device is an octal transparent latch coupled to
eight 3-State output buffers. The two sections of the device are
controlled independently by Enable (E) and Output Enable (OE
control gates. The 74ABT573A is functionally identical to the
74ABT373 but has a flow-through pinout configuration to facilitate
PC board layout and allow easy interface with microprocessors.
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE
independent of the latch operation.
When OE
outputs. When OE
is Low, the latched or transparent data appears at the
is High, the outputs are in the High-impedance
”OFF” state, which means they will neither drive nor load the bus.
CONDITIONS
= 25°C; GND = 0V
T
amb
CC
CC
) controls all eight 3-State buffers
TYPICAL UNIT
2.8
3.3
3 pF
6 pF
)
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic DIP –40°C to +85°C 74ABT573A N 74ABT573A N SOT146-1
20-Pin plastic SO –40°C to +85°C 74ABT573A D 74ABT573A D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74ABT573A DB 74ABT573A DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT573A PW 74ABT573APW DH SOT360-1
PIN CONFIGURA TION
1
OE
2
D0
3
D1
4
D2
5
D3
D4
6
D5
7
D6
8
D7
9
GND
10 11
20
V
CC
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
E
PIN DESCRIPTION
PIN
NUMBER
1 OE Output enable input (active-Low)
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17,
16, 15, 14,
13, 12
11 E Enable input (active-High)
10 GND Ground (0V)
20 V
SYMBOL FUNCTION
D0-D7 Data inputs
Q0-Q7 Data outputs
Positive supply voltage
CC
SA00185
1995 Sep 06 853–1455 15703
1
Page 2
Philips Semiconductors Product specification
Octal D-type transparent latch (3-State)
LOGIC SYMBOL (IEEE/IEC)
1
EN
11
C1
2
2D 1
3
4
5
6
7
8
9
FUNCTION TABLE
INPUTS INTERNAL OUTPUTS OPERATING MODE
OE E Dn REGISTER Q0 – Q7
L
L
L
L
L L X NC NC Hold
H
H
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low E transition
H
H
↓
↓
L
H
Dn
L
H
l
h
X
NC
Dn
19
18
17
16
15
14
13
12
SA00187
L
H
L
H
L
H
L
H
Z
Z
Enable and read register
Latch and read register
Disable outputs
LOGIC SYMBOL
11
E
1
OE
74ABT573A
23456789
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 18 17 16 15 14 13 12
SA00186
LOGIC DIAGRAM
D0
2
11
E
1
OE
1995 Sep 06
D
EQ
Q0
D1
3
D
EQ
19
Q1
D2
4
D
EQ
18
Q2
D3
5
D
EQ
17
Q3
D4
6
D
EQ
16
Q4
D5
7
D
EQ
15
Q5
D6
8
D
EQ
14
Q6
D7
9
D
EQ
13
12
Q7
SA00188
2
Page 3
Philips Semiconductors Product specification
Octal D-type transparent latch (3-State)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
DC output current output in Low state 128 mA
Storage temperature range –65 to 150 °C
PARAMETER CONDITIONS RATING UNIT
3
3
1, 2
–1.2 to +7.0 V
output in Off or High state –0.5 to +5.5 V
74ABT573A
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
Min Max
V
CC
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 5 ns/V
T
amb
DC supply voltage 4.5 5.5 V
Input voltage 0 V
I
High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
High-level output current –32 mA
Low-level output current 64 mA
Operating free-air temperature range –40 +85 °C
CC
V
1995 Sep 06
3
Page 4
Philips Semiconductors Product specification
Octal D-type transparent latch (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS T
V
V
V
V
RST
I
OFF
IPU/I
I
OZH
I
OZL
I
CEX
I
CCH
I
CCL
I
CCZ
∆I
I
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
IK
VCC = 4.5V; IOH = –3mA; VI = VIL or V
High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V
OH
VCC = 4.5V; IOH = –32mA; VI = VIL or V
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
OL
Power-up output low
3
voltage
I
Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
I
VCC = 5.5V; IO = 1mA; VI = GND or V
IH
IH
IH
IH
CC
Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
Power-up/down 3-State
PD
output current
4
3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
O
Output current
1
Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V
VCC = 2.0V; VO = 0.5V; VOE = Don’t Care;
= GND or V
V
I
CC
IH
IH
CC
VCC = 5.5V; VO = 2.5V –40 –180 –40 –180 mA
VCC = 5.5V; Outputs High, VI = GND or V
CC
CC
VCC = 5.5V; Outputs 3-State;
= GND or V
V
Additional supply current per
CC
input pin
2
I
VCC = 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
transition time of up to 100µsec is permitted.
between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V 10%, a
CC
= +25°C
amb
Min Typ Max Min Max
2.5 2.9 2.5 V
3.0 3.4 3.0 V
2.0 2.4 2.0 V
0.42 0.55 0.55 V
0.13 0.55 0.55 V
±5.0 ±50 ±50 µA
5.0 50 50 µA
–5.0 –50 –50 µA
5.0 50 50 µA
100 250 250 µA
24 30 30 mA
100 250 250 µA
0.5 1.5 1.5 mA
74ABT573A
T
= –40°C
amb
to +85°C
UNIT
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL PARAMETER WA VEFORM
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
1995 Sep 06
Propagation delay
Dn to Qn
Propagation delay
E to Qn
Output enable time
to High and Low level
Output disable time
from High and Low level
2
1
4
5
4
5
LIMITS
T
T
amb
V
= +25oC
= +5.0V
CC
amb
= +5.0V ±0.5V
V
CC
Min Typ Max Min Max
1.5
2.2
1.2
1.8
1.2
2.7
1.5
1.2
2.8
3.3
2.5
3.0
3.0
3.8
2.8
2.2
4.0
4.8
4.0
4.4
4.5
5.3
4.1
3.4
1.5
2.2
1.2
1.8
1.2
2.7
1.5
1.2
4
= -40 to
o
+85
C
4.5
5.3
4.5
4.7
5.2
5.7
4.5
3.8
UNIT
ns
ns
ns
ns
Page 5
Philips Semiconductors Product specification
ÉÉÉ
ÉÉÉ
Octal D-type transparent latch (3-State)
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL PARAMETER WA VEFORM
ts(H)
(L)
t
s
th(H)
(L)
t
h
tw(H)
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
Setup time, High or Low
Dn to E
Hold time, High or Low
Dn to E
E pulse width
High
E
Qn
V
M
t
PHL
tw(H)
3
3
1 2.0 0.7 2.0 ns
V
M
V
M
V
M
t
PLH
V
M
LIMITS
T
amb
V
CC
= +25oC
= +5.0V
T
= -40 to +85oC
amb
= +5.0V ±0.5V
V
CC
Min Typ Min
1.0
1.0
1.0
1.0
OE
Qn
0.3
0.2
–0.1
–0.2
1.0
1.0
1.0
1.0
V
M
t
PZH
V
M
V
M
74ABT573A
UNIT
t
PHZ
VOH–0.3V
0V
ns
ns
SA00063
Waveform 1. Propagation Delay, Enable to Output, and Enable
Pulse Width
Dn
Qn
V
M
t
PLH
V
M
t
PHL
V
M
V
M
SA00064
Waveform 2. Propagation Delay for Data to Outputs
V
Dn
t
(H)
s
E
NOTE: The shaded areas indicate when the input is permitted
V
M
M
t
(H)
h
V
M
to change for predictable output performance.
V
V
M
M
(L)
t
s
t
(L)
h
V
M
SA00065
Waveform 3. Data Setup and Hold Times
SA00066
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OE
Qn
V
M
t
PZL
V
M
t
PLZ
V
M
VOL+0.3V
V
OL
SA00332
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
1995 Sep 06
5
Page 6
Philips Semiconductors Product specification
Octal D-type transparent latch (3-State)
TEST CIRCUIT AND WAVEFORM
V
CC
R
OUT
L
R
L
of
PULSE
GENERATOR
V
IN
R
D.U.T.
T
V
OUT
C
L
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
= Load capacitance includes jig and probe capacitance;
C
L
see AC CHARACTERISTICS for value.
= Termination resistance should be equal to Z
R
T
pulse generators.
74ABT573A
t
90%
7.0V
NEGATIVE
PULSE
POSITIVE
PULSE
10%
V
M
10% 10%
t
THL
t
TLH
90% 90%
V
M
Input Pulse Definition
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude Rep. Rate t
74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns
W
(tF)
(tR)t
t
W
90%
V
M
V
M
10%
VM = 1.5V
t
W
R
t
TLH
THL
AMP (V)
0V
(tR)
(tF)
AMP (V)
0V
t
F
SA00012
1995 Sep 06
6
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