Page 1
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
1
December 15, 1994 853-1775 14470
FEATURES
•Metastable immune characteristics
•Pin compatible with 74F74 and 74F5074
•Typical f
MAX
= 200MHz
•Output skew guaranteed less than 2.0ns
•High source current (I
OH
= 15mA) ideal for clock driver
applications
•Output capability: +20mA/–15mA
•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (S
Dn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. Data must be stable
just one setup time prior to the low-to-high transition of the clock for
guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive-going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
The 74ABT5074 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the
74ABT5074 are:
τ ≅ 94ps and T
o
≅ 1.3 × 10
7
sec
where τ represents a function of the rate at which a latch in a
metastable state resolves that condition and T
0
represents a
function of the measurement of the propensity of a latch to enter a
metastable state.
PIN CONFIGURA TION
14
13
12
11
10
9
87
6
5
4
3
2
1
GND
V
CC
SD1
Q1
Q1
CP1
R
D1
D1
R
D0
D0
Q
0
CP0
SD0
Q0
SA00001
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
2, 12 D0, D1 Data inputs
3, 11 CP0, CP1 Clock inputs (active rising edge)
4, 10 SD0, SD1 Set inputs (active-Low)
1, 13 RD0, RD1 Reset inputs (active-Low)
5, 9 Q0, Q1
Data outputs (active-Low),
non-inverting
6, 8 Q0, Q1
Data outputs (active-Low),
inverting
7 GND Ground (0V)
14 V
CC
Positive supply voltage
QUICK REFERENCE DA TA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay
CPn to Qn or Qn
CL = 50pF; VCC = 5V
2.8
2.4
ns
C
IN
Input capacitance VI = 0V or V
CC
3 pF
I
CC
Total supply current Outputs disabled; VCC =5.5V 2 µA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
14-pin plastic DIP –40°C to +85°C 74ABT5074N SOT27-1
14-pin plastic SOL –40°C to +85°C 74ABT5074D SOT108-1
14-pin plastic shrink small outline SSOP Type II –40°C to +85°C 74ABT5074DB SOT337-1
14-pin plastic thin shrink small outline (TSSOP) Type I –40°C to +85°C 74ABT5074PW SOT402-1
Page 2
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
December 15, 1994
2
LOGIC SYMBOL
Q0 Q0 Q1 Q1
5 6 9 8
VCC = Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0 D1
2 12
SA00002
IEC/IEEE SYMBOL
4
3
2
1
10
11
12
13
5
6
9
8
S
S
C1
C2
R
1D
2D
R
SA00003
LOGIC DIAGRAM
VCC = Pin 14
GND = Pin 7
5, 9
6, 8
Q
Q
4, 10
1, 13
3, 11
2, 12
S
D
R
D
CP
D
SF00048
FUNCTION TABLE
INPUTS OUTPUTS
OPERATING
SD RD CP D Q Q
MODE
L H X X H L Asynchronous set
H L X X L H Asynchronous reset
L L X X L H Undetermined*
H H ↑ h H L Load ”1”
H H ↑ l L H Load ”0”
H H ↑ X NC NC Hold
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low-to-high clock
transition
L = Low voltage level
l = Low voltage level one setup time prior to low-to-high clock
transition
NC= No change from the previous setup
X = Don’t care
↑ = Low-to-high clock transition
↑
= Not low-to-high clock transition
* = This setup is unstable and will change when either set or
reset return to the high level
Page 3
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
December 15, 1994
3
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term ‘metastable immune’ to
describe characteristics of some of the products in its family. By
running two independent signal generators (see Figure 1) at nearly
the same frequency (in this case 10MHz clock and 10.02MHz data)
the device-under-test can often be driven into a metastable state. If
the Q output is then used to trigger a digital scope set to infinite
persistence the Q
output will build a waveform. An experiment was
run by continuously operating the devices in the region where
metastability will occur.
D Q
Q
CP
TRIGGER
DIGITAL
SCOPE
INPUT
SIGNAL
GENERATOR
SA00004
SIGNAL
GENERATOR
Figure 1. Test Setup
After determining the T
0
and τ of the flop, calculating the mean time
between failures (MTBF) is simple. Suppose a designer wants to
use the 74ABT5074 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74ABT5074 7 nanoseconds after the clock
edge. He simply plugs his number into the following equation:
MTBF = e
(t’/τ)
/ TO*fC*f
I
In this formula, fC is the frequency of the clock, fI is the average
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ > h, h being the normal propagation delay). In
this situation the f
I
will be twice the data frequency of 20 MHz
because input events consist of both of low and high transitions.
Multiplying f
I
by fC gives an answer of 10
15
Hz2. From Figure 2 it is
clear that the MTBF is greater than 10
10
seconds. Using the above
formula the actual MTBF is 1.69 × 10
10
seconds or about 535 years.
E6 E8 E10 E12 E14 E15 = fc*fi
E13
E12
E11
E10
E9
E8
E7
E6
E5
10,000 YEARS
100 YEARS
ONE YEAR
ONE WEEK
MTBF
(SECONDS)
t’ (NANOSECONDS)
4 5 6 7 8
MTBF = e
(t’/τ)
/TO*fC*f
I
SA00005
VCC = 5V, T
amb
= 25°C, τ =94ps, To = 1.3x107 sec
Figure 2. Mean Time Between Failures (MTBF) versus t’
Page 4
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
December 15, 1994
4
TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCCS AND TEMPERA TURES
T
amb
= –40°C T
amb
= 25°C T
amb
= 85°C
V
CC
τ T
0
τ T
0
τ T
0
5.5V 84ps 1.0 × 106 sec 93ps 3.8 × 106 sec 89ps 1.5 × 109 sec
5.0V 84ps 2.7 × 108 sec 94ps 1.3 × 107 sec 106ps 2.2 × 106 sec
4.5V 89ps 1.0 × 109 sec 103ps 2.1 × 107 sec 115ps 4.4 × 106 sec
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL PARAMETER CONDITIONS RATING UNIT
V
CC
DC supply voltage –0.5 to +7.0 V
I
IK
DC input diode current VI < 0 –18 mA
V
I
DC input voltage
3
–1.2 to +7.0 V
I
OK
DC output diode current VO < 0 –50 mA
V
OUT
DC output voltage
3
Output in Off or High state –0.5 to +5.5 V
I
OUT
DC output current Output in Low state 40 mA
T
stg
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN MAX
UNIT
V
CC
DC supply voltage 4.5 5.5 V
V
I
Input voltage 0 V
CC
V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level Input voltage 0.8 V
I
OH
High-level output current –15 mA
I
OL
Low-level output current 20 mA
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
Page 5
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
December 15, 1994
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C T
amb
= –40°C to +85°C
UNIT
MIN TYP MAX MIN MAX
V
IK
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
V
OH
High-level output voltage
VCC = 4.5V; IOH = –15mA;
V
I
= VIL or V
IH
2.5 2.9 2.5 V
V
OL
Low-level output voltage
VCC = 4.5V; IOL = 20mA;
V
I
= VIL or V
IH
0.35 0.5 0.5 V
I
I
Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
I
OFF
Power-off leakage current VCC = 0.0V; VO or VI 4.5V ±5.0 ±100 ±100 µA
I
O
Output current
1
VCC = 5.5V; VO = 2.5V –50 –75 –180 –50 –180 mA
I
CC
Quiescent supply current VCC = 5.5V; VI = GND or V
CC
2 50 50 µA
∆I
CC
Additional supply current
per input pin
2
VCC = 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.25 500 500 µA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25°C
V
CC
= +5.0V
T
amb
= –40 to +85°C
V
CC
= +5.0V ±0.5V
UNIT
MIN TYP MAX MIN MAX
f
max
Maximum clock frequency 1 180 250 150 ns
t
PLH
t
PHL
Propagation delay
CPn to Qn or Q
n
1
1.0
1.0
2.8
2.4
3.9
3.5
1.0
1.0
4.5
3.7
ns
t
PLH
t
PHL
Propagation delay
S
Dn, RDn to Qn or Qn
2
1.0
1.0
3.5
3.1
4.6
4.2
1.0
1.0
5.5
4.7
ns
t
sk(o)
Output skew
1, 2
CPn to Qn to Qn
4 1.5 2.0 ns
NOTES:
1. | t
PN
actual - tPM actual | for any output compared to any other output where N and M are either LH or HL.
2. Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.).
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25°C
V
CC
= +5.0V
T
amb
= –40 to +85°C
V
CC
= +5.0V ±0.5V
UNIT
MIN TYP MIN
ts(H)
t
s
(L)
Setup time, High or Low
Dn to CPn
1
2.5
2.5
1.5
1.5
2.5
2.5
ns
th(H)
t
h
(L)
Hold time, High or Low
Dn to CPn
1
0
0
–1.4
–1.4
0
0
ns
t
w
(H)
t
w
(L)
CPn pulse width,
high or low
1
1.5
2.4
0.6
1.8
1.5
2.9
ns
t
w
(L) SDn or RDn pulse width, low 2 2.0 1.3 2.2 ns
t
rec
Recovery time
S
Dn or RDn to CPn
3 2.4 1.3 2.8 ns
Page 6
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
December 15, 1994
6
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
The shaded areas indicate when the input is permitted to change for the predictable output performance.
ÉÉÉ
ÉÉÉ
ÉÉÉ
V
M
V
M
t
PLH
t
PHL
Qn
V
M
Dn
V
M
V
M
V
M
V
M
V
M
CPn
ts(L) th(L) ts(H) th(H)
V
M
tw(H)
V
M
V
M
Qn
f
MAX
tw(L)
t
PLH
t
PHL
SA00008
Waveform 1. Propagation Delay for Data to Output,
Data Setup Time and Hold Time, and Clock Width
V
M
SDn
V
M
Qn
t
w
(L)
V
M
t
PLH
RDn
Qn
V
M
t
PHL
V
M
V
M
tw(L)
V
M
t
PHL
V
M
t
PLH
SA00009
Waveform 2. Propagation Delay for Set and Reset to Output,
Set and Reset Pulse Width
SA00010
V
M
V
M
t
REC
SDn or RDn
CPn
Waveform 3. Recovery Time for Set or Reset to Output
SA00011
V
M
V
M
tSK(0)
Qn, Qn
Q
n, Qn
Waveform 4. Output Skew
Page 7
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
December 15, 1994
7
TEST CIRCUIT AND WAVEFORM
t
w
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
NEGATIVE
PULSE
POSITIVE
PULSE
t
w
AMP (V)
0V
0V
t
THL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
R
t
F
1MHz 500ns
2.5ns 2.5ns
Input Pulse Definition
V
CC
FAMILY
74F
D.U.T.
PULSE
GENERATOR
R
L
C
L
R
T
V
IN
V
OUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
t
THL (tf
)
t
TLH (tr
)
t
TLH (tr
)
AMP (V)
amplitude
3.0V
SA00058
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