Datasheet 74ABT374CSJX, 74ABT374CSJ, 74ABT374CSCX, 74ABT374CSC, 74ABT374CPC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS011510 www.fairchildsemi.com

November 1992
Revised November 1999

74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs

74ABT374
Octal D-Type Flip-Flop with 3-ST ATE Outputs

General Description

The ABT374 is an octal D-typ e flip-flop featuring separate
D-type inputs for each flip-flop and 3-STATE outputs for
bus-oriented applicatio ns. A buffered Clock (CP) and Out­put Enable (OE

) are common to all flip-flops.

Features

■ Edge-triggered D-type inputs

■ Buffered positive edge-triggered cl ock

■ 3-STATE outputs for bus-oriented applications

■ Output sink capability of 64 mA, source capability of

32 mA

■ Guaranteed output skew

■ Guaranteed multiple output switching specifications

■ Output switching sp ecified for both 50 pF and 250 pF

loads

■ Guaranteed simultaneous switching, noise level and
dynamic threshold performan ce

■ Guarante ed latchup pr otection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram Pin Descriptions

Order Number Package Number Package Description

74ABT374CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT374CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT374CPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

D

0–D7

Data Inputs
CP Clock Pulse Input (Active Rising Edge)
OE

3-STATE Output Enable Input (Active LOW)
O

0–O7

3-STATE Outputs

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74ABT374

Functional Description

The ABT374 consi sts of ei gh t e dge -tr igge re d flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Outp ut Enable are com mon to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE

) LOW, the contents of the

eight flip-flops ar e available at the outputs. When OE

is
HIGH, the outputs are in a high impeda nce state. Opera­tion of the OE

input does not affect t he state of the flip-

flops.

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance



= LOW-to-HIGH Transition

NC = No Change

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Internal Outputs Function

OE CP D Q O

H H L NC Z Hold
H H H NC Z Hold
H



L L Z Load

H



H H Z Load

L



L L L Data Available

L



H H H Data Available
L H L NC NC No Change in Data
L H H NC NC No Change in Data

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74ABT374

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired . Functional operation
under these conditions is not implied.

Note 2: Either voltage lim it or c urrent limit is sufficient to protect inputs

DC Electrical Characteristics

Note 3: For 8-bit toggling, I

CCD

<0.8 mA/MHz.

Note 4: Guaranteed, but not tested.

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to

Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State −0.5V to 5.5V

in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the r ated I

OL

(mA)

DC Latchup Source Current:

OE

Pin

−150 mA
(Across Comm Operating Range)
Other Pins −500 mA

Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns
Clock Input 100mV/ns

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

V

OH

Output HIGH Voltage 2.5 V Min IOH = −3 mA

2.0 V Min IOH = −32 mA
V

OL

Output LOW Voltage 0.55 V Min IOL = 64 mA

I

IH

Input HIGH Current 1

µA Max

VIN = 2.7V (Note 4)

1V

IN

= V

CC

I

BVI

Input HIGH Current Breakdown Test 7 µA MaxVIN = 7.0V

I

IL

Input LOW Current −1

µA Max

VIN = 0.5V (Note 4)

−1V

IN

= 0.0V

V

ID

Input Leakage Test 4.75 V 0.0 IID = 1.9 µA, All Other Pins Grounded

I

OZH

Output Leakage Current 10 µA 0 − 5.5V

V

OUT

= 2.7V; OE = 2.0V

I

OZL

Output Leakage Current −10 µA 0 − 5.5V

V

OUT

= 0.5V; OE = 2.0V

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

= 0.0V

I

CEX

Output High Leakage Current 50 µA MaxV

OUT

= V

CC

I

ZZ

Bus Drainage Test 100 µA 0.0V

OUT

= 5.5V; All Others VCC or GND

I

CCH

Power Supply Current 50 µA Max All Outputs HIGH

I

CCL

Power Supply Current 30 mA Max All Outputs LOW

I

CCZ

Power Supply Current 50 µA Max

OE = VCC; All Others at VCC or GND

I

CCT

Additional ICC/Input Outputs Enabled 2.5 mA VI = VCC − 2.1V

Outputs 3-STATE 2.5 mA Max Enable Input VI = VCC − 2.1V
Outputs 3-STATE 2.5 mA Data Input VI = VCC − 2.1V

All Others at VCC or GND

I

CCD

Dynamic I

CC

No Load mA/

Max

Outputs OPEN

(Note 4) 0.30

MHz

OE = GND, (Note 3)
One Bit Toggling, 50% Duty Cycle

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74ABT374

DC Electrical Characteristics

(SOIC package)

Note 5: Max number of output s d ef ined as (n). n − 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested.
Note 6: Max number of output s d ef ined as (n). n − 1 data input s are driven 0V to 3V. One output HIGH. Guaranteed, but not te s te d.
Note 7: Max number of data inpu ts (n) swit chin g. n − 1 in pu ts swit chin g 0V t o 3V. Input-under-te st sw itchin g: 3V to thres hold (V

ILD

), 0V to threshold (V

IHD

).

Guaranteed, but not tested.

AC Electrical Characteristics

(SOIC and SSOP Package)

AC Operating Requirements

Symbol Parameter Min Typ Max Units

V

CC

Conditions

CL = 50 pF, RL = 500Ω

V

OLP

Quiet Output Maximum Dynamic V

OL

0.5 0.8 V 5.0 TA = 25°C (Note 5)

V

OLV

Quiet Output Minimum Dynamic V

OL

−1.3 −0.9 V 5.0 TA = 25°C (Note 5)

V

OHV

Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 6)

V

IHD

Minimum HIGH Level Dynamic Input Voltage 2.0 1.6 V 5.0 TA = 25°C (Note 7)

V

ILD

Maximum LOW Level Dynamic Input Voltage 1.3 0.8 V 5.0 TA = 25°C (Note 7)

Symbol Parameter

TA = +25°C

T

A

= −55°C to

+125°C

T

A

= −40°C to +85°C

Units

V

CC

= +5.0V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

f

MAX

Maximum Clock Frequency 150 200 150 150 MHz

t

PLH

Propagation Delay 2.0 3.2 5.0 1.4 6.6 2.0 5.0

ns

t

PHL

CP to O

n

2.0 3.3 5.0 2.0 7.6 2.0 5.0

t

PZH

Output Enable Time 1.5 3.1 5.3 0.8 5.7 1.5 5.3

ns

t

PZL

1.5 3.1 5.3 1.5 7.2 1.5 5.3

t

PHZ

Output Disable Time 1.5 3.6 5.4 1.3 7.2 1.5 5.4

ns

t

PLZ

1.5 3.4 5.4 1.0 7.0 1.5 5.4

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = −40°C to +85°C

Units

V

CC

= +5.0V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Max Min Max Min Max

tS(H) Setup Time, HIGH 1.5 2.5 1.0

ns

t

S

(L) or LOW Dn to CP 1.5 2.5 1.5

tH(H) Hold Time, HIGH 1.0 2.5 1.0

ns

t

H

(L) or LOW Dn to CP 1.0 2.5 1.0

t

W

(H) Pulse Width, CP 3.0 3.3 3.0

ns

tW(L) HIGH or LOW 3.0 3.3 3.0

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74ABT374

Extended AC Electrical Characteristics

(SOIC Package)

Note 8: This specification is guar anteed but not tested . Th e lim it s apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 9: This specification is guar anteed but not tested . Th e lim its represent propagation delay with 25 0 pF load capacitors in plac e of the 50 pF load capac­itors in the standard AC load. This specification pertains to single output switching only.

Note 10: This specific at ion is guaranteed but n ot te s te d. T he limits represent propagation delays for all paths described sw it c hing in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.

Note 11: The 3-STATE delay Time is dominated by th e R C net w ork (500Ω, 250 pF) on the output and ha s been excluded from t he datasheet.

Skew (Note 16)

(SOIC Package)

Note 12: This spec ification is guara nteed but no t tested. The lim its represen t propagation de lays with 250 pF load capac itors in place o f the 50 pF load
capacitors in the standard AC load.

Note 13: This describ es th e d ifferenc e b etw een t he del ay o f t he LO W-to -HIGH an d the HIGH -to -LOW tra nsitio n on t he s ame p in. It is mea sure d across all
the outputs (drivers) on t he same chip, the worst (largest delta) numb er is the guaranteed specification. This specification is guaranteed but not tested.

Note 14: Skew is def ined as the absolu te valu e of the differ ence be tween the actu al propag ation de lays f or any tw o separ ate outpu ts of the sam e devi ce.
The specification appli es t o an y ou tput s sw itchi ng HIGH -to -LO W (t

OSHL

), LOW-to-HIGH (t

OSLH

), or any combination switching LOW-to-HIGH and/or HIGH-

to-LOW (t

OST

). This specificatio n is guaranteed but not te s te d.

Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and V

CC

) from device to device. This specification is guaranteed but not
tested.
Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase

(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Capacitance

Note 17: C

OUT

is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.

Symbol Parameter

TA = −40°C to +85°CT

A

= −40°C to +85°CT

A

= −40°C to +85°C

Units

V

CC

= 4.5V to 5.5V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V

CL = 50 pF CL = 250 pF CL = 250 pF

8 Outputs Switching (Note 9) 8 Outputs Switching

(Note 8) (Note 10)

Min Max Min Max Min Max

t

PLH

Propagation Delay 1.5 5.7 2.0 7.8 2.0 10.0

ns

t

PHL

CP to O

n

1.5 5.7 2.0 7.8 2.0 10.0

t

PZH

Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5

ns

t

PZL

1.5 6.2 2.0 8.0 2.0 10.5

t

PHZ

Output Disable Time 1.0 5.5

(Note 11) (Note 11) ns

t

PZL

1.0 5.5

Symbol Parameter

TA = −40°C to +85°CT

A

= −40°C to +85°C

Units

VCC = 4.5V–5.5V VCC = 4.5V–5.5V

CL = 50 pF CL = 250 pF

8 Outputs Switching 8 Outputs Switching

(Note 12) (Note 13)

Max Max

t

OSHL

Pin to Pin Skew

1.0 1.8 ns

(Note 14) HL Transitions
t

OSLH

Pin to Pin Skew

1.0 1.8 ns

(Note 14) LH Transitions
t

PS

Duty Cycle

1.8 4.3 ns

(Note 13) LH–HL Skew
t

OST

Pin to Pin Skew

2.0 4.3 ns

(Note 14) LH/HL Transitions
t

PV

Device to Device Skew

2.5 4.6 ns

(Note 15) LH/HL Transitions

Symbol Parameter Typ Units

Conditions
(TA = 25°C)

C

IN

Input Capacitance 5.0 pF VCC = 0V

C

OUT

(Note 17) Output Capacitance 9.0 pF VCC = 5.0V

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74ABT374

AC Loading

*Includes jig and pr obe capacitance

FIGURE 1. Standard AC Test Load

FIGURE 2. V

M

= 1.5V

Input Pulse Requirements

FIGURE 3. Test Input Signal Requirements

AC Waveforms

FIGURE 4. Propagation Delay Waveforms for

Inverting and Non-Inverting Functions

FIGURE 5. Propagation Delay,

Pulse Width Waveforms

FIGURE 6. 3-STA TE Output HIGH

and LOW Enable and Disable Times

FIGURE 7. Setup Time, Hold Time

and Recovery Time Waveforms

Amplitude Rep. Rate t

w

t

r

t

f

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

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74ABT374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74ABT374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74ABT374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Num b er MSA20

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74ABT374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

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74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MO-001, 0.300” Wide

Package Number N20A

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Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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