Datasheet 74ABT374APW, 74ABT374AN, 74ABT374ADB, 74ABT374AD Datasheet (Philips)

Philips Semiconductors Product specification

Octal D-type flip-flop; positive-edge trigger (3-State)

FEA TURES

•8-bit positive edge triggered register

•3-State output buffers

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power-up 3-State

•Power-up reset

•Live insertion/extraction permitted

QUICK REFERENCE DAT A

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

IN

Propagation delay CP to Qn

Input capacitance VI = 0V or V Output capacitance Outputs disabled; VO = 0V or V Total supply current Outputs disabled; VCC =5.5V 110 µA

CL = 50pF; VCC = 5V

DESCRIPTION

The 74ABT374A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT374A is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE gates.

The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE independent of the clock operation.

When OE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus.

T

is Low, the stored data appears at the outputs. When OE

CONDITIONS = 25°C; GND = 0V

amb

CC

74ABT374A

) control

) controls all eight 3-State buffers

TYPICAL UNIT

3.4

3.8 4 pF 7 pF

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

20-Pin Plastic DIP –40°C to +85°C 74ABT374A N 74ABT374A N SOT146-1 20-Pin plastic SO –40°C to +85°C 74ABT374A D 74ABT374A D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74ABT374A DB 74ABT374A DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT374A PW 74ABT374APW DH SOT360-1

PIN CONFIGURA TION

1

OE

2

Q0

3

D0

4

D1

5

Q1

6

Q2

7

D2

8

D3

9

Q3 Q4

10 11

GND

20

V

CC

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13 12

CP

SA00110

PIN DESCRIPTION

NUMBER

1 OE Output enable input (active-Low)

3, 4, 7, 8,

13, 14, 17,

18

2, 5, 6, 9,

12, 15, 16,

19 11 CP Clock pulse input (active rising edge) 10 GND Ground (0V) 20 V

SYMBOL FUNCTION

D0-D7 Data inputs

Q0-Q7 Data outputs

Positive supply voltage

CC

1995 Sep 06 853-1448 15704

1

Philips Semiconductors Product specification

INTERNAL

OPERATING MODE

Latch

Disabl

Octal D-type flip-flop; positive-edge trigger (3-State)

LOGIC SYMBOL

3 4 7 8 13 14 1817

D0 D1 D2 D3 D4 D5 D6 D7

CP

11

OE

1

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

SA00111

FUNCTION TABLE

INPUTS

OE CP Dn

INTERNAL REGISTER

L ↑ l L L L ↑ h H H

L ↑ X NC NC Hold H ↑ X NC Z H ↑ Dn Dn Z

H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition

= not a Low-to-High clock transition

↑

OUTPUTS

Q0 – Q7

LOGIC SYMBOL (IEEE/IEC)

and read register

e outputs

74ABT374A

1

11

32 45 76

89 13 12 14 15 17 16 18 19

EN C1

1D

SA00112

LOGIC DIAGRAM

D0

11

CP

1

OE

1995 Sep 06

D1

3 4 7 8 13 14 17 18

D

CP Q

Q0

D

CP Q

2 5 6 9 12 15 16 19

D2

D

CP Q

Q1 Q2 Q3 Q4 Q5 Q6 Q7

D3

D

CP Q

D4

D

CP Q

D5

D

CP Q

D6

D

CP Q

D7

2

D

CP Q

SA00113

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

Octal D-type flip-flop; positive-edge trigger (3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

I

V

I V

I

OK OUT

OUT

T

CC IK

stg

DC supply voltage –0.5 to +7.0 V DC input diode current VI < 0 –18 mA DC input voltage

I

DC output diode current VO < 0 –50 mA DC output voltage DC output current output in Low state 128 mA Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

3

RECOMMENDED OPERATING CONDITIONS

V

CC

V V V I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 10 ns/V

T

amb

DC supply voltage 4.5 5.5 V Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

High-level output current –32 mA Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

1, 2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

LIMITS

MIN MAX

74ABT374A

CC

V

1995 Sep 06

3

Philips Semiconductors Product specification

Octal D-type flip-flop; positive-edge trigger (3-State)

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER TEST CONDITIONS T

MIN TYP MAX MIN MAX

V

I

OFF

IPU/I

I

OZH

I

OZL

I

CEX

I

CCH

I

CCL

I

CCZ

∆I

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

OH

VCC = 4.5V; IOH = –32mA; VI = VIL or V

Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

OL

Power-up output low voltage3VCC = 5.5V; IO = 1mA; VI = GND or V

RST

I

Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA

I

IH

CC

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State

PD

output current 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V

3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V Output High leakage current VCC = 5.5V; VO = 0.5V; VI = GND or V

I

O

Output current

1

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

VCC = 0.0V; IO = 1mA; VI = GND or VCC;

= Don’t Care

V

OE

IH

CC

VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA VCC = 5.5V; Outputs High, VI = GND or V

CC

VCC = 5.5V; Outputs 3–State;

= GND or V

V

Additional supply current per

CC

input pin

2

I

VCC = 5.5V; one input at 3.4V, other inputs at V

CC

or GND

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

= +25°C

amb

2.5 2.9 2.5 V

3.0 3.4 3.0 V

2.0 2.4 2.0 V

0.42 0.55 0.55 V

0.13 0.55 0.55 V

±5.0 ±50 ±50 µA

5.0 50 50 µA

–5.0 –50 –50 µA

5.0 50 50 µA

110 250 250 µA

24 30 30 mA

110 250 250 µA

0.5 1.5 1.5 mA

74ABT374A

T

= –40°C

amb

to +85°C

UNIT

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

1995 Sep 06

Maximum clock frequency 1 200 300 200 ns Propagation delay

CP to Qn Output enable time

to High and Low level Output disable time

from High and Low level

1 3

4 3

4

LIMITS

T

amb

V

= +25oC = +5.0V

CC

amb

= +5.0V ±0.5V

V

CC

Min Typ Max Min Max

1.7

2.0

1.2

2.2

1.8

1.5

3.4

3.8

3.5

4.3

3.6

3.0

4.5

4.9

4.5

5.4

4.7

4.1

1.7

2.0

1.2

2.2

1.8

1.5

4

= -40 to

o

+85

C

5.1

5.2

5.4

6.2

5.2

4.3

UNIT

ns

Philips Semiconductors Product specification

Octal D-type flip-flop; positive-edge trigger (3-State)

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

ts(H)

(L)

t

s

th(H)

(L)

t

h

tw(H)

(L)

t

w

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

Setup time, High or Low Dn to CP

Hold time, High or Low Dn to CP

CP pulse width High or Low

CP

VM VM VM

2

1

1/f

MAX

LIMITS

T

amb

V

CC

= +25oC = +5.0V

T

= -40 to +85oC

amb

= +5.0V ±0.5V

V

CC

Min Typ Min

1.5

1.2

1.0

2.0

2.8

OE

0.6

0.3

–0.3 –0.5

0.8

1.0

1.5

1.2

1.0

2.0

2.8

V

M

V

M

74ABT374A

UNIT

ns

tw(H) tw(L)

Qn

t

PHL

VM VM

t

PLH

SA00056

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

V

Dn

t

(H) th(H) ts(L) th(L)

s

CP

NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.

V

M

V

M

V

M

V

M

SA00107

Waveform 2. Data Setup and Hold Times

Qn

t

PZH

V

t

PHZ

M

VOH–0.3V

0V

SA00066

Waveform 3. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

OE

Qn

V

M

t

PZL

V

M

t

PLZ

V

M

VOL+0.3V

0V

SA00067

Waveform 4. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

1995 Sep 06

5

Philips Semiconductors Product specification

Octal D-type flip-flop; positive-edge trigger (3-State)

TEST CIRCUIT AND WAVEFORM

V

CC

R

OUT

L

R

L

of

PULSE

GENERATOR

V

IN

R

D.U.T.

T

V

OUT

C

L

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t t

PLZ PZL

closed closed

All other open

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

74ABT374A

t

90%

7.0V NEGATIVE

PULSE

POSITIVE PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

Amplitude Rep. Rate t

74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns

W

(tF)

(tR)t

t

W

90%

V

M

V

M

10%

VM = 1.5V

t

W

R

t

TLH

THL

AMP (V)

0V

(tR)

(tF)

AMP (V)

0V

t

F

SA00012

1995 Sep 06

6