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INTEGRATED CIRCUITS
74ABT373A
Octal transparent latch (3-State)
Product specification 1995 Feb 17
IC23 Data Handbook
Page 2
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
FEA TURES
•8-bit transparent latch
•3-State output buffers
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•Power-up 3-State
•Power-up reset
•Live insertion/extraction permitted
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
Dn to Qn
Input capacitance VI = 0V or V
Output capacitance Outputs disabled; VO = 0V or V
Total supply current Outputs disabled; VCC =5.5V 100 µA
DESCRIPTION
The 74ABT373A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT373A device is an octal transparent latch coupled to
eight 3-State output buffers. The two sections of the device are
controlled independently by Enable (E) and Output Enable (OE
control gates.
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE
independent of the latch operation.
When OE
outputs. When OE
“OFF” state, which means they will neither drive nor load the bus.
CONDITIONS
= 25°C; GND = 0V
T
amb
CL = 50pF; VCC = 5V
CC
) controls all eight 3-State buffers
is Low, the latched or transparent data appears at the
is High, the outputs are in the High-impedance
TYPICAL UNIT
3.2
3.6
ns
4 pF
CC
7 pF
)
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic DIP –40°C to +85°C 74ABT373A N 74ABT373A N SOT146-1
20-Pin plastic SO –40°C to +85°C 74ABT373A D 74ABT373A D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74ABT373A DB 74ABTD373A B SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT373A PW 7ABT373APW DH SOT360-1
PIN CONFIGURATION
1
OE
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3 Q4
10 11
GND
20
V
CC
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13
12
E
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enable input (active-Low)
3, 4, 7, 8, 13,
14, 17, 18
2, 5, 6, 9, 12,
15, 16, 19
11 E Enable input (active-High)
10 GND Ground (0V)
20 V
D0-D7 Data inputs
Q0-Q7 Data outputs
Positive supply voltage
CC
SA00059
1995 Feb 17 853-1454 14852
2
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Philips Semiconductors Product specification
OPERATING
74ABT373AOctal transparent latch (3-State)
LOGIC SYMBOL
3 4 7 8 13 14 1817
D0 D1 D2 D3 D4 D5 D6 D7
11
E
1
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
SA00060
FUNCTION TABLE
INPUTS
OE E Dn
LLHHL
LL↓↓l
H
h
INTERNAL
REGISTER
L
H
L
H
L L X NC NC Hold
HHLHX
Dn
NC
Dn
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E
transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E
transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low E transition
OUTPUTS
Q0 – Q7
L
H
L
H
Z
Z
OPERATING
MODE
Enable and read
register
Latch and read
register
Disable outputs
LOGIC SYMBOL (IEEE/IEC)
1
11
32
45
76
89
13 12
14 15
17 16
18 19
EN
C1
1D
SA00061
LOGIC DIAGRAM
1995 Feb 17
OE
D0
3 4 7 8 13 14 17 18
D
E Q
11
E
1
D1
D
EQ
2 5 6 9 12 15 16 19
Q0
D2
D
EQ
Q1 Q2 Q3 Q4 Q5 Q6 Q7
D3
D
EQ
D4
D
EQ
D5
D
EQ
D6
D
EQ
D7
D
EQ
SA00062
3
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
74ABT373AOctal transparent latch (3-State)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
DC output current output in Low state 128 mA
Storage temperature range –65 to 150 °C
PARAMETER CONDITIONS RATING UNIT
3
3
1, 2
–1.2 to +7.0 V
output in Off or High state –0.5 to +5.5 V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
Min Max
V
CC
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 5 ns/V
T
amb
DC supply voltage 4.5 5.5 V
Input voltage 0 V
I
High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
High-level output current –32 mA
Low-level output current 64 mA
Operating free-air temperature range –40 +85 °C
CC
V
1995 Feb 17
4
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Philips Semiconductors Product specification
Quiescent su ly current
74ABT373AOctal transparent latch (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
SYMBOL PARAMETER TEST CONDITIONS T
amb
= +25°C
Min Typ Max Min Max
V
V
V
V
I
OFF
IPU/I
I
OZH
I
OZL
I
CEX
I
CCH
I
CCL
I
CCZ
∆I
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
IK
VCC = 4.5V; IOH = –3mA; VI = VIL or V
High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V
OH
VCC = 4.5V; IOH = –32mA; VI = VIL or V
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
OL
Power-up output low
RST
I
I
3
voltage
Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
VCC = 5.5V; IO = 1mA; VI = GND or V
IH
IH
IH
IH
CC
2.5 2.9 2.5 V
3.0 3.4 3.0 V
2.0 2.4 2.0 V
0.3 0.55 0.55 V
0.13 0.55 0.55 V
Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
Power-up/down 3-State
PD
output current
3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
I
O
Output current
1
Quiescent supply current
Additional supply current per
CC
input pin
2
VCC = 2.0V; VO = 0.5V; VOE = Don’t Care V
= GND or V
CC
1
IH
IH
CC
±5.0 ±50 ±50 µA
0.1 50 50 µA
–0.1 –50 –50 µA
5.0 50 50 µA
VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or V
VCC = 5.5V; Outputs Low, VI = GND or V
VCC = 5.5V; Outputs 3-State;
= GND or V
V
I
CC
VCC = 5.5V; one input at 3.4V,
other inputs at V
or GND
CC
CC
CC
100 250 250 µA
24 30 30 mA
100 250 250 µA
0.5 1.5 1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V .
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
amb
to +85°C
UNIT
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL PARAMETER WAVEFORM
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
1995 Feb 17
Propagation delay
Dn to Qn
Propagation delay
E to Qn
Output enable time
to High and Low level
Output disable time
from High and Low level
LIMITS
T
= -40 to
T
amb
V
= +25oC
= +5.0V
CC
amb
+85
= +5.0V ±0.5V
V
CC
o
C
UNIT
Min Typ Max Min Max
2
1
4
5
4
5
1.4
1.4
1.4
1.9
1.2
2.1
1.3
1.2
3.2
3.6
3.2
3.7
3.1
4.2
3.4
3.0
4.2
4.7
4.2
4.8
4.2
5.2
4.6
4.1
1.4
1.4
1.4
1.9
1.2
2.1
1.3
1.2
4.7
5.1
4.8
5.1
5.1
5.7
5.1
4.3
ns
ns
ns
ns
5
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Philips Semiconductors Product specification
ÉÉÉ
ÉÉÉ
74ABT373AOctal transparent latch (3-State)
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
T
SYMBOL PARAMETER WAVEFORM
ts(H)
(L)
t
s
th(H)
(L)
t
h
tw(H)
Setup time, High or Low
Dn to E
Hold time, High or Low
Dn to E
E pulse width
High
3
3
1 2.5 1.7 2.5 ns
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
= +25oC
amb
= +5.0V
V
CC
Min Typ Min
1.5
1.0
1.0
1.0
0.7
0.4
0.0
–0.5
T
= -40 to +85oC
amb
= +5.0V ±0.5V
V
CC
1.5
1.0
1.0
1.0
UNIT
ns
ns
Qn
E
V
M
tw(H)
t
PHL
V
M
V
M
V
M
t
PLH
V
M
SA00063
Waveform 1. Propagation Delay, Enable to Output, and Enable
Pulse Width
Dn
Qn
V
M
t
PLH
V
M
t
PHL
V
M
V
M
SA00064
Waveform 2. Propagation Delay for Data to Outputs
OE
Qn
V
M
t
PZH
V
M
t
PHZ
V
M
VOH–0.3V
0V
SA00066
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OE
Qn
V
M
t
PZL
V
M
t
PLZ
V
M
VOL+0.3V
0V
SA00067
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Dn
E
1995 Feb 17
V
V
M
M
t
(H)
s
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
t
(H)
h
V
M
V
V
M
M
(L)
t
s
V
M
Waveform 3. Data Setup and Hold Times
t
(L)
h
SA00065
6
Page 7
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
TEST CIRCUIT AND WAVEFORM
V
CC
R
PULSE
GENERATOR
V
IN
R
D.U.T.
T
V
OUT
C
L
L
R
L
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
= Load capacitance includes jig and probe capacitance;
C
L
see AC CHARACTERISTICS for value.
= Termination resistance should be equal to Z
R
T
pulse generators.
OUT
of
t
W
(tF)
(tR)t
t
W
90%
V
M
V
M
10%
7.0V
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
V
M
10% 10%
t
THL
t
TLH
90% 90%
V
M
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude Rep. Rate t
t
W
R
74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns
t
TLH
THL
AMP (V)
0V
(tR)
(tF)
AMP (V)
0V
t
F
SA00012
1995 Feb 17
7
Page 8
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1995 Feb 17
8
Page 9
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
1995 Feb 17
9
Page 10
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
1995 Feb 17
10
Page 11
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1995
All rights reserved. Printed in U.S.A.
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