Datasheet 74ABT2952CSPC, 74ABT2952CSCX, 74ABT2952CSC, 74ABT2952CMTCX, 74ABT2952CMTC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS010969 www.fairchildsemi.com

January 1992
Revised November 1999

74ABT2952 Octal Registered Transceiver

74ABT2952
Octal Registered Transceiver

General Description

The ABT2952 is an octal registered transce iver. Two 8-bit
back to back registe rs stor e dat a flowi ng in both direct ions
between two bidirectional buses. Separate clock, clock
enable and 3-STATE output enable signals are provided for
each register. The output pins are guaranteed to source 32
mA and to sink 64 mA.

Features

■ Separate clock, clock enable and 3-STATE output
enable provided for each register

■ A and B output sink capability of 64 mA source capability
of 32 mA

■ Guaranteed output skew

■ Guaranteed multiple output switching specifications

■ Output switching specifie d for both 50 pF and 250 pF

loads

■ Guaranteed simultaneous switching noise level and
dynamic threshold performan ce

■ Guaranteed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Nondestructive hot insertion capability

Ordering Code:

Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Pin Descriptions

Order Number Package Numb er Package Description

74ABT2952CSC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT2952CMSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT2952CMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

A

0–A7

A-Register Inputs/B-Register
3-STATE Outputs

B

0–B7

B-Register Inputs/A-Register
3-STATE Outputs

OEA

Output Enable A-Register
CPA A-Register Clock
CEA

A-Register Clock Enable
OEB

Output Enable B-Register
CPB B-Register Clock
CEB

B-Register Clock Enable

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74ABT2952

Truth Table

Output Control

Register Function Table (Applies to A or B Register)

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance



= LOW-to-HIGH Transition

NC = No Change

Block Diagram

OE

Internal

Output Function

Q

H X Z Disable Outputs
LLLEnable Outputs
LHH

Inputs Internal

Function

DCPCEQ

X X H NC Hold Data
L



L L Load Data

H



LH

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74ABT2952

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired . Functional operation
under these conditions is not implied.

Note 2: Either voltage lim it or c urrent limit is sufficient to pro te c t in puts.

DC Electrical Characteristics

Note 3: Guaranteed, but not tested.
Note 4: For 8-bit toggling, I

CCD

< 1.4 mA/MHz.

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disable or
Power-Off State −0.5V to +5.5V
in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)
DC Latchup Source Current −500 mA
Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns
Clock Input 100 mV/ns

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins)

V

OH

Output HIGH Voltage 2.5 IOH = −3 mA (An, Bn)

2.0 IOH = −32 mA (An, Bn)

V

OL

Output LOW Voltage 0.55 V Min IOL = 64 mA (An, Bn)

V

ID

Input Leakage Test 4.75 V 0.0 IID = 1.9 µA (Non-I/O Pins)

All Other Pins Grounded

I

IH

Input HIGH Current 1

µAMax

VIN = 2.7V (Non-I/O Pins) (Note 3)

1V

IN

= VCC (Non-I/O Pins)

I

BVI

Input HIGH Current Breakdown Test 7 µAMaxVIN = 7.0V (Non-I/O Pins)

I

BVIT

Input HIGH Current Breakdown Test (I/O) 100 µAMaxVIN = 5.5V (An, Bn)

I

IL

Input LOW Current −1

µAMax

VIN = 0.5V (Non-I/O Pins) (Note 3)

−1V

IN

= 0.0V (Non-I/O Pins)

I

IH

+ I

OZH

Output Leakage Current 10 µA0V–5.5V V

OUT

= 2.7V (An, Bn);

OEA

or OEB = 2.0V

I

IL

+ I

OZL

Output Leakage Current −10 µA0V–5.5V V

OUT

= 0.5V (An, Bn);

OEA

or OEB = 2.0V

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

= 0V (An, Bn)

I

CEX

Output HIGH Leakage Current 50 µAMaxV

OUT

= VCC (An, Bn)

I

ZZ

Bus Drainage Test 100 µA0.0VV

OUT

= 5.5V (An, Bn);

All Others GND

I

CCH

Power Supply Current 250 µA Max All Outputs HIGH

I

CCL

Power Supply Current 30 mA Max All Outputs LOW

I

CCZ

Power Supply Current 50 µA Max Outputs 3-STATE;

All Others GND

I

CCT

Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V; All Others

at VCC or GND

I

CCD

Dynamic I

CC

No Load 0.18 mA/MHz Max Outputs Open

(Note 4)

OEA or OEB = GND,
Non-I/O = GND or V

CC

One Bit toggling, 50% duty cycle
(Note 4)

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74ABT2952

DC Electrical Characteristics

(SOIC Package)

Note 5: Max number of output s d ef ined as (n). n − 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested.
Note 6: Max number of output s d ef ined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inpu ts (n) swit chin g. n − 1 in pu ts swit chin g 0V t o 3V. Input-under-te st sw itchin g: 3V to thres hold (V

ILD

), 0V to threshold (V

IHD

).

Guaranteed, but not tested.

AC Electrical Characteristics

(SOIC and SSOP Package)

AC Operating Requirements

Symbol Parameter Min Typ Max Units

V

CC

Conditions

CL = 50 pF,

R

L

= 500Ω

V

OLP

Quiet Output Maximum Dynamic V

OL

0.6 0.8 V 5.0 TA = 25°C (Note 5)

V

OLV

Quiet Output Minimum Dynamic V

OL

−1.2 −1.0 V 5.0 TA = 25°C (Note 5)

V

OHV

Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 6)

V

IHD

Minimum HIGH Level Dynamic Input Voltage 2.0 1.7 V 5.0 TA = 25°C (Note 7)

V

ILD

Maximum LOW Level Dynamic Input Voltage 1.2 0.8 V 5.0 TA = 25°C (Note 7)

Symbol Parameter

T

A

= +25°CT

A

= −40°C to +85°C

Units

V

CC

= +5.0V VCC = 4.5V to 5.5V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

f

MAX

Maximum Clock Frequency 200 200 MHz

t

PLH

Propagation Delay 1.5 3.4 5.3 1.5 5.3

ns

t

PHL

CPA or CPB to 1.5 3.6 5.3 1.5 5.3
An or B

n

t

PZH

Output Enable Time 1.5 3.2 5.5 1.5 5.5

ns

t

PZL

OEA or OEB to

1.5 3.5 5.5 1.5 5.5

A

n

or B

n

t

PHZ

Output Disable Time 1.5 3.6 6.0 1.5 6.0

ns

t

PLZ

OEA or OEB to

1.5 3.2 6.0 1.5 6.0

A

n

or B

n

Symbol Parameter

TA = +25°CT

A

= −40°C to +85°C

Units

VCC = +5.0V VCC = 4.5V to 5.5V

C

L

= 50 pF CL = 50 pF

Min Max Min Max

t

S

(H) Setup Time, HIGH 2.5 2.5

ns

ts(L) or LOW An or B

n

2.5 2.5

to CPA or CPB

tH(H) Hold Time, HIGH 1.5 1.5

ns

tH(L) or LOW An or B

n

1.5 1.5

to CPA or CPB

tS(H) Setup Time, HIGH 2.5 2.5

ns

tS(L)

or LOW CEA or CEB

2.5 2.5

to CPA or CPB

tH(H) Hold Time, HIGH 1.5 1.5

ns

tH(L)

or LOW CEA or CEB

1.5 1.5

to CPA or CPB

tW(H) Pulse Width, 3.0 3.0

ns

tW(L) HIGH or LOW 3.0 3.0

CPA or CP B

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74ABT2952

Extended AC Electrical Characteristics

(SOIC Package)

Note 8: This specification is guar anteed but not tested. Th e lim it s apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 9: This specification is guar anteed but not tested. Th e lim it s represent propagation delay with 250 pF load capacitors in place of the 5 0 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.

Note 10: This specific at ion is guaranteed but not te s te d. T he limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.

Note 11: The 3-STATE delays are dominated by the RC ne twork (500Ω, 250 pF) on the out put and has been exclud ed from the datashee t.

Skew

(SOIC Package)

Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 13: This spec ification is guara nteed but no t tested. The lim its represen t propagation de lays with 250 pF load capacitors in place o f the 50 pF load
capacitors in the standard AC load.

Note 14: Skew is def ined as the absolu te valu e of the differ ence be tween the actu al propag ation de lays f or any tw o separ ate outpu ts of the sam e devi ce.
The specification applies to any outputs switching HIGH-to-LOW (t

OSHL

), LOW to HIGH (t

OSLH

), or any combi nat io n swi tc hin g LO W- to -H IGH an d/ or HIGH- to -

LOW (t

OST

). This specification is guaranteed but not tested.

Note 15: This describ es th e d ifferenc e b etw een t he del ay o f t he LO W-to -HIGH an d the HIGH -to -LOW tra nsitio n on t he s ame p in. It is mea sure d across all
the outputs (drivers) on t he same chip, the worst (la rgest delta) number is the guaranteed specificat ion. This specification is guaranteed but not tested.

Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and V

CC

) from device to device. This specification is guaranteed but not

tested.

Capacitance

Note 17: C

I/O

is measured at frequency f = 1 MHz, per MIL-STD - 883, Method 3012.

Symbol Parameter

TA = −40°C to +85°CTA = −40°C to +85°CTA = −40°C to +85°C

Units

V

CC

= 4.5V to 5.5V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V
CL = 50 pF CL = 250 pF CL = 250 pF

8 Outputs Switching (Note 9) 8 Outputs Switching

(Note 8) (Note 10)

Min Max Min Max Min Max

t

PLH

Propagation Delay 1.5 6.0 2.0 8.0 2.5 10.5

ns

t

PHL

CPA or CPB to An or B

n

1.5 6.0 2.0 8.0 2.5 10.5

t

PZH

Output Enable Time 1.5 6.0 2.0 8.0 2.5 11.5

ns

t

PZL

OEA or OEB to An or B

n

1.5 6.0 2.0 8.0 2.5 11.5

t

PHZ

Output Disable Time 1.5 6.0

(Note 11) (Note 11) ns

t

PZL

OEA or OEB to An or B

n

1.5 6.0

Symbol Parameter

TA = −40°C to +85°CT

A

= −40°C to +85°C

Units

V

CC

= 4.5V–5.5V VCC = 4.5V–5.5V

CL = 50 pF CL = 250 pF

8 Outputs Switching 8 Outputs Switching

(Note 12) (Note 13)

Max Max

t

OSHL

Pin to Pin Skew

1.0 1.5 ns

(Note 14) HL Transitions
t

OSLH

Pin to Pin Skew

1.0 2.0 ns

(Note 14) LH Transitions
t

PS

Duty Cycle

2.0 4.5 ns

(Note 15) LH–HL Skew
t

OST

Pin to Pin Skew

2.1 4.5 ns

(Note 14) LH/HL Transitions
t

PV

Device to Device Skew

2.5 5.0 ns

(Note 16) LH/HL Transitions

Symbol Parameter Typ Units

Conditions

TA = 25°C

C

IN

Input Capacitance 5 pF VCC = 0V (Non I/O Pins)

C

I/O

(Note 17) Output Capacitance 11 pF VCC = 5.0V (An, Bn)

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74ABT2952

AC Loading

*Includes jig and pr obe capacitance

FIGURE 1. Standard AC Test Load

FIGURE 2. Test Input Signal Levels

FIGURE 3. Input Signal Requirements

AC Waveforms

FIGURE 4. Propagation Delay Waveforms for

Inverting and Non-Inverting Functions

FIGURE 5. Propagation Delay,

Pulse Width Waveforms

FIGURE 6. 3-STA TE Output HIGH

and LOW Enable and Disable Times

FIGURE 7. Setup Time, Hold Time

and Recovery Time Waveforms

Amplitude Rep. Rate t

W

t

r

t

f

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

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74ABT2952

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M24B

24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Num b er MSA24

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74ABT2952 Octal Registered Transceiver

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC24

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component in any compon ent of a lif e supp ort
device or system whose failure t o perform can be rea­sonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.

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