Datasheet 74ABT16501CMTDX, 74ABT16501CMTD, 74ABT16501CCW, 74ABT16501CSSCX, 74ABT16501CSSC Datasheet (Fairchild Semiconductor)

January 1995
Revised January 1999

74ABT16501 18-Bit Universal Bus Transceivers with 3-STATE Outputs

© 1999 Fairchild Semiconductor Corporation DS011690.prf www.fairchildsemi.com

74ABT16501
18-Bit Universal Bus Transceivers with 3-STATE Outputs

General Description

The ABT16501 18-bit u niversal bus transceiver combines
D-type latches and D-type flip-flops to allow data flow in
transparent, latched, and clocked modes.

Data flow in each direction is contr olled by output-enable
(OEAB and OEBA

), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. F or A- to-B data flo w, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CLKAB. Output-enable OEAB is active-high.
When OEAB is HIGH, the outputs are active. When OEAB
is LOW, the outputs are in the high-impedance state.

Data flow for B to A is similar to tha t of A to B but uses
OEBA

, LEBA, and CL KBA. The output e nables are com-

plementary (OEAB is active HIGH and OEBA

is active

LOW).
To ensure the high-imp edance state during power up or

power down, OE inputs should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver.

Features

■ Combines D-Type latches and D-Type flip-flops for oper­ation in transparent, latched, or clocked mode

■ Flow-through architecture optimizes PCB layout

■ Guaranteed latch-up protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

Ordering Code:

Devices also available in Tape or Reel. Specify by appending t he suffix letter “X” to the ordering code.

Connection Diagram

Pin Assign ment for SSOP

Function Table (Note 1)

Note 1: A-to-B data flow is s hown: B-to-A flow is similar but use s OEBA,

LEBA, and CLKBA.
Note 2: Output level before the indicated s teady-state input conditions

were established.
Note 3: Output level before the indicated s teady-state input conditions

were established, provided tha t CL KAB was HIGH before LEAB went LOW.

Order Number Package Number Package Description

74ABT16501CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16501CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Inputs Output

OEAB LEAB CLKAB A B

LXXX Z
HHXL L
HHXH H
HL↑ LL
HL↑ HH
HLHXB

0

(Note 2)

HLLXB

0

(Note 3)

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74ABT16501

Logic Diagram

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74ABT16501

Absolute Maximum Ratings(Note 4)

Recommended Operating
Conditions

Note 4: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation
under these condit ions is not implied.

Note 5: Either voltage limit or current limi t is s uf f ic ient to protect inputs.

DC Electrical Characteristics

Note 6: Guaranteed, but not tested.

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to

Ground Pin −0.5V to +7.0V
Input Voltage (Note 5) −0.5V to +7.0V
Input Current (Note 5) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disabled or

Power-off State −0.5V to 5.5V

in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

DC Latchup Source Current −500 mA
Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

V

OH

Output HIGH Voltage 2.5 V Min IOH = −3 mA

2.0 V Min IOH = −32 mA

V

OL

Output LOW Voltage 0.55 V Min IOL = 64 mA

I

IH

Input HIGH Current 1 µAMaxVIN = 2.7V (Note 6)

1V

IN

= V

CC

I

BVI

Input HIGH Current Breakdown Test 7 µAMaxVIN = 7.0V

I

IL

Input LOW Current −1 µAMaxVIN = 0.5V (Note 6)

−1V

IN

= 0.0V

V

ID

Input Leakage Test 4.75 V 0.0 IID = 1.9 µA

All Other Pins Grounded

IIH + Output Leakage Current

10 µA0 − 5.5V

V

OUT

= 2.7V; OE, OE = 2.0V

I

OZH

IIL + Output Leakage Current

−10 µA0 − 5.5V

V

OUT

= 0.5V; OE, OE = 2.0V

I

OZL

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

= 0V

I

CEX

Output HIGH Leakage Current 50 µAMaxV

OUT

= V

CC

I

ZZ

Bus Drainage Test 100 µA0.0V

OUT

= 5.5V; All Others GND

I

CCH

Power Supply Current 1.0 mA Max All Outputs HIGH

I

CCL

Power Supply Current 68 mA Max An or Bn Outputs LOW

I

CCZ

Power Supply Current

1.0 mA Max

OEn = VCC,
All Others at VCC or GND

I

CCT

Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V

All Others at VCC or GND

I

CCD

Dynamic I

CC

No Load mA/ Max Outputs Open

(Note 6) 0.23 MHz Transparent Mode

One Bit Toggling, 50% Duty Cycle

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74ABT16501

DC Electrical Characteristics

Note 7: Max number of outputs defined as (n) . n − 1 dat a inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not te s te d.
Note 8: Max number of outputs defined as (n) . n − 1 dat a inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 9: Max number of data i npu ts (n) swit chin g. n − 1 inpu ts switc hing 0 V to 3 V. Input-under-test switc hing: 3V t o thr esho ld (V

ILD

), 0V to threshold (V

IHD

).

Guaranteed, but not tes t ed.

AC Electrical Charac teristics

AC Operating Requirements

Symbol Parameter Min Typ Max Units

V

CC

Conditions

CL = 50 pF; RL = 500Ω

V

OLP

Quiet Output Maximum Dynamic V

OL

0.7 1.2 V 5.0 TA = 25°C (Note 7)

V

OLV

Quiet Output Minimum Dynamic V

OL

−1.5 −1.0 V 5.0 TA = 25°C (Note 7)

V

OHV

Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 8)

V

IHD

Minimum HIGH Level Dynamic Input Voltage 2.2 1.8 V 5.0 TA = 25°C (Note 9)

V

ILD

Maximum LOW Level Dynamic Input Voltage 1.2 0.8 V 5.0 TA = 25°C (Note 9)

Symbol Parameter

TA = +25°CT

A

= −40°C to +85°C

Units

VCC = +5V VCC = 4.5V–5.5V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

f

max

Maximum Clock Frequency 150 200 150 MHz

t

PLH

Propagation Delay 1.0 2.7 4.6 1.0 4.6 ns

t

PHL

A or B to B or A 1.0 3.2 4.6 1.0 4.6

t

PLH

Propagation Delay 1.0 3.1 5.0 1.0 5.0 ns

t

PHL

LEAB or LEBA to B or A 1.0 3.6 5.5 1.0 5.5

t

PLH

Propagation Delay 1.0 3.4 5.3 1.0 5.3 ns

t

PHL

CLKAB or CLKBA to B or A 1.0 3.7 5.3 1.0 5.3

t

PZH

Propagation Delay 1.5 2.7 5.6 1.5 5.6 ns

t

PZL

OEAB or OEBA to B or A

1.5 3.0 5.6 1.5 5.6

t

PHZ

Propagation Delay 1.5 3.7 6.0 1.5 6.0 ns

t

PLZ

OEAB or OEBA to B or A

1.5 3.2 6.0 1.5 6.0

Symbol Parameter

TA = +25°CT

A

= −40°C to +85°C

Units

VCC = +5V VCC = 4.5V–5.5V

CL = 50 pF CL = 50 pF

Min Max Min Max

tS(H) Setup Time, 4.0 4.0 ns
tS(L) A to CLKAB, B to CLKBA 4.0 4.0
tH(H) Hold Time, 0 0 ns
tH(L) A to CLKAB, B to CLKBA 0 0
tS(H) Setup Time, A to LEAB 4.0 4.0 ns
tS(L)

or B to LEBA, CLK HIGH

4.0 4.0

tH(H) Hold Time, A to LEAB 1.5 1.5 ns
tH(L)

or B to LEBA, CLK HIGH

1.5 1.5

tS(H) Setup Time, A to LEAB 1.5 1.5 ns
ts(L)

or B to LEBA, CLK LOW

1.5 1.5

tH(H) Hold Time, A to LEAB 1.5 1.5

ns

tH(L)

or B to LEBA, CLK LOW

1.5 1.5

tW(H) Pulse Width, 3.3 3.3 ns
tW(L) LEAB or LEBA, HIGH 3.3 3.3
tW(H) Pulse Width, CLKAB 3.3 3.3 ns
tW(L) or CLKBA, HIGH or LOW 3.3 3.3

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74ABT16501

Capacitance

Note 10: C

I/O

is measured at frequency f = 1 MHz per MIL-STD-883, Method 3012.

AC Loading

*Includes jig and prob e c apacitance.

FIGURE 1. Standard AC Test Load

FIGURE 2. V

M

= 1.5V

Input Pulse Requirement s

FIGURE 3. Test Input Signal Requirements

AC Waveforms

FIGURE 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions

FIGURE 5. Propagation Delay,

Pulse Width W aveforms

FIGURE 6. 3-STATE Output HIGH

and LOW Enable and Disable Times

FIGURE 7. Setup Time, Hold Time

and Recovery Time Waveforms

Symbol Parameter Typ Units

Conditions

TA = 25°C

C

IN

Input Capacitance 5.0 pF VCC = 0.0V

C

I/O

(Note 10) Output Capacitance 11.0 pF VCC = 5.0V

Amplitude Rep. Rate t

W

t

r

t

f

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

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74ABT16501

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

Package Number MS56A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reser ves the right at any time without notice to change said circuitry and specifications.

74ABT16501 18-Bit Universal Bus Transceivers with 3-STATE Outputs

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant injur y to the
user.

2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r ea­sonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD56