Datasheet 74ABTH16500CDL, 74ABTH16500CDGG, 74ABT16500CDL, 74ABT16500CDGG Datasheet (Philips)

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74ABT16500C
74ABTH16500C

18-bit universal bus transceiver (3-State)

Product specification
Supersedes data of 1997 Jun 12
IC23 Data Handbook

1998 Feb 27

INTEGRATED CIRCUITS

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

2

1998 Feb 27 853-1800 19027

FEA TURES

•18-bit bidirectional bus interface

•3-State buffers

•74ABTH16500C incorporates bus-hold data inputs which

eliminate the need for external pull-up resistors to hold unused
inputs

•Output capability: +64mA/-32mA

•TTL input and output switching levels

•Live insertion/extraction permitted

•Power-up reset

•Power-up 3-State

•Negative edge-triggered clock inputs

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

•Flexible operation permits 18 embedded D-type latches or

flip-flops to operate in clocked, transparent, or latched modes.

DESCRIPTION

The 74ABT16500C is a high-performance BiCMOS Device which
combines low static and dynamic power dissipation with high speed
and high output drive.

This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA

), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CPAB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA

,

LEBA and CPBA

. The output enables are complimentary (OEAB is

active High, and OEBA is active Low).
Active bus-hold circuitry is provided to hold unused or floating data

inputs at a valid logic level.
Two options are available, 74ABT16500C which does not have the

bus-hold feature and 74ABTH16500C which incorporates the
bus-hold feature.

QUICK REFERENCE DA TA

SYMBOL PARAMETER

CONDITIONS

T

amb

= 25°C; GND = 0V

TYPICAL UNIT

t

PLH

t

PHL

Propagation delay
An to Bn or Bn to An

CL = 50pF;
VCC = 5V

2.1

1.7

ns

C

IN

Input capacitance (Control pins) VI = 0V or V

CC

3 pF

C

I/O

I/O pin capacitance Outputs disabled; V

I/O

= 0V or V

CC

7 pF

I

CCZ

pp

Outputs disabled; VCC = 5.5V 500 µA

I

CCL

Quiescent su ly current

Outputs low; VCC = 5.5V 8 mA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16500C DL BT16500C DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16500C DGG BT16500C DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16500C DL BH16500C DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16500C DGG BH16500C DGG SOT364-1

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

1998 Feb 27

3

LOGIC SYMBOL

3 5 6 8 9 10121314151617192021232426

A0 A1 A2 A3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17A4

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17

54 52 51 49 47 45 44 43 42 41 40 38 37 36 34 33 3148

1

2
55
27
28
30

CPBA

LEBA

OEBA

CPAB

LEAB

OEAB

SA00322

PIN CONFIGURA TION

GND

GND

GND

GND

LEAB

OEAB

GND

V

CC

V

CC

GND GND

V

CC

V

CC

GND

GND

GND

LEBA

OEBA

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

A0

A1
A2

A3
A4
A5

A6
A7
A8

A9
A10
A11

A12
A13
A14

A15
A16

A17

CPAB
B0

B2

B1

B3
B4
B5

B6
B7
B8
B9
B10
B11

B12
B13
B14

B15
B16

B17
CPBA

SW00035

LOGIC SYMBOL (IEEE/IEC)

EN1

2C3
C3
G2
EN4

5C6
C6
G5

3D 1 1
416D

1
55
2

27
30
28

3

5
6
8

9
10
12

13
14
15
16
17
19
20
21
23
24
26

54

52
51
49
48

47
45
44
43
42
41
40
38
37
36
34
33
31

SH00087

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

1998 Feb 27

4

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

1 OEAB A-to-B Output enable input

27 OEBA B-to-A Output enable input (active low)

2, 28 LEAB/LEBA A-to-B/B-to-A Latch enable input

55,30 CPAB/CPBA A-to-B/B-to-A Clock input (active falling edge)

3, 5, 6, 8, 9, 10, 12, 13, 14, 15,

16, 17, 19, 20, 21, 23, 24, 26

A0-A17 Data inputs/outputs (A side)

54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31

B0-B17 Data inputs/outputs (B side)

4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)

7, 22, 35, 50 V

CC

Positive supply voltage

FUNCTION TABLE

INPUTS

Internal

OUTPUTS

OPERATING MODE

OEAB LEAB CPAB An

Registers

Bn

L H X X X Z Disabled
L ↓ X h H Z
L ↓ X I L Z

Disabled, Latch data

L L H or L X NC Z Disabled, Hold data
L L ↓ h H Z
L L ↓ I L Z

Disabled, Clock data

H H X H H H

p

H H X L L L

Transparent

H ↓ X h H H

p

H ↓ X I L L

Latch data & displa

y

H L ↓ h H H

p

H L ↓ I L L

Clock data & displa

y

H L H or L X H H

p

H L H or L X L L

Hold data & displa

y

NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level

h = High voltage level one set-up time prior to the Enable or Clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don’t care
Z = High Impedance “off” state
↓ = High-to-Low Enable or Clock transition

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

1998 Feb 27

5

LOGIC DIAGRAM

C1

ID

ID

C1

OEAB

LEAB

CLKAB

CLKBA

OEBA

LEBA

1

2

55

30

28

27

54

B1

To 17 other channels

A1

3

CLK

CLK

SW00234

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

1998 Feb 27

6

ABSOLUTE MAXIMUM RATINGS

1, 2

SYMBOL

PARAMETER CONDITIONS RATING UNIT

V

CC

DC supply voltage –0.5 to +7.0 V

I

IK

DC input diode current VI < 0 –18 mA

V

I

DC input voltage

3

–1.2 to +7.0 V

I

OK

DC output diode current VO < 0 –50 mA

V

OUT

DC output voltage

3

Output in Off or High state –0.5 to +5.5 V

p

Output in Low state 128

I

OUT

DC output current

Output in High state –64

mA

T

stg

Storage temperature range –65 to +150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

PARAMETER LIMITS

SYMBOL

MIN MAX

UNIT

V

CC

DC supply voltage 4.5 5.5 V

V

I

Input voltage 0 V

CC

V

V

IH

High-level input voltage 2.0 V

V

IL

Input voltage 0.8 V

I

OH

High-level output current –32 mA

I

OL

Low-level output current 64 mA

∆t/∆v Input transition rise or fall rate; Outputs enabled 10 ns/V

T

amb

Operating free-air temperature range –40 +85 °C

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

1998 Feb 27

7

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

T

amb

= +25°C

T

amb

= –40°C

to +85°C

UNIT

MIN TYP MAX MIN MAX

V

IK

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.8 –1.2 –1.2 V

VCC = 4.5V; IOH = –3mA; VI = VIL or V

IH

2.5 2.9 2.5 V

V

OH

High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

IH

3.0 4.0 3.0 V

VCC = 4.5V; IOH = –32mA; VI = VIL or V

IH

2.0 2.4 2.0 V

V

OL

Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

IH

0.35 0.55 0.55 V

V

RST

Power-up output voltage

3

VCC = 5.5V; IO = 1mA; VI = GND or V

CC

0.13 0.55 0.55 V

V

= 5.5V; V

= GND or

III

nput leakage curren

t

V

CC

5.5V V

I

GND or

5.5V

Control pi

ns 0.

011.01.0µA

VCC = 4.5V; VI = 0.8V 35 35

I

HOLD

Bus Hold current A and B
Ports6 74ABTH16500C

VCC = 4.5V; VI = 2.0V –75 –75

µA

VCC = 5.5V; VI = 0 to 5.5V ±800

I

OFF

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V 2 100 100 µA

I

PU/PD

Power-up/down 3-State
output current

4

VCC = 2.1V; VO = 0.0V or VCC;
VOE = Don’t care

2 50 50 µA

IIH + I

OZH

3-State output High current VCC = 5.5V; VO = 5.5V; VI = VIL or V

IH

1.0 10 10 µA

IIL + I

OZL

3-State output Low current VCC = 5.5V; VO = 0.0V; VI = VIL or V

IH

–1.0 –10 –10 µA

I

CEX

Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V

CC

2 50 50 µA

I

O

Output current

1

VCC = 5.5V; VO = 2.5V –50 –80 –180 –50 –180 mA

I

CCH

VCC = 5.5V; Outputs High, VI = GND or
V

CC

0.5 2 2 mA

I

CCL

Quiescent supply current VCC = 5.5V; Outputs Low , VI = GND or V

CC

8 19 19 mA

I

CCZ

VCC = 5.5V; Outputs 3–State;
VI = GND or V

CC

0.5 2 2 mA

∆I

CC

Additional supply current
per input pin

2

74ABT16500C

VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND

5.0 50 50 µA

∆I

CC

Additional supply current
per input pin

2

74ABTH16500C

VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND

200 500 500 µA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V .

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V

CC

between 0V and 2.1V , with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a

transition time of up to 100µsec is permitted.

5. Unused pins at V

CC

or GND.

6. This is the bus hold overdrive current required to force the input to the opposite logic state.

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

1998 Feb 27

8

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

SYMBOL PARAMETER WAVEFORM

T

amb

= +25oC

VCC = +5.0V

T

amb

= –40 to +85oC

VCC = +5.0V ±0.5V

UNIT

MIN TYP MAX MIN MAX

f

max

Maximum clock frequency 1 150 225 150 MHz

t

PLH

t

PHL

Propagation delay
An to Bn or Bn to An

2

1.0

1.0

2.1

1.7

3.0

2.5

1.0

1.0

3.4

3.0

ns

t

PLH

t

PHL

Propagation delay
LEAB to Bn or LEBA to An

3

1.0

1.0

3.2

2.8

4.3

3.7

1.0

1.0

4.9

4.0

ns

t

PLH

t

PHL

Propagation delay
CPAB to Bn or CPBA to An

1

1.0

1.0

3.4

2.6

4.5

3.5

1.0

1.0

5.3

4.6

ns

t

PZH

t

PZL

Output enable time
to HIGH and LOW level

5
6

1.0

1.5

3.3

2.4

4.4

3.2

1.0

1.5

5.0

3.9

ns

t

PHZ

t

PLZ

Output disable time
from HIGH and LOW level

5
6

1.5

1.4

3.3

2.5

4.3

3.3

1.5

1.4

5.3

3.9

ns

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

SYMBOL PARAMETER WAVEFORM

T

amb

= +25oC

V

CC

= +5.0V

T

amb

= –40 to +85oC

V

CC

= +5.0V ±0.5V

UNIT

MIN TYP MIN

ts(H)
ts(L)

Setup time, HIGH or LOW
An to CPAB or Bn to CPBA

4

2.0

2.0

0.7

0.6

2.0

2.0

ns

th(H)
th(L)

Hold time, HIGH or LOW
An to CPAB or Bn to CPBA

4

0.7

0.7

–0.5
–0.8

0.7

0.7

ns

ts(H)
t

s

(L)

Setup time, HIGH or LOW
An to LEAB or Bn to LEBA

4

2.0

2.0

0.1

0.1

2.0

2.0

ns

th(H)
th(L)

Hold time HIGH or LOW
An to LEAB or Bn to LEBA

4

0.7

0.7

–0.1
–0.1

0.7

0.7

ns

t

w

Pulse width, HIGH or LOW
CPAB or CPBA

1 3 1.2 3 ns

tw(H)

Pulse width, HIGH
LEAB or LEBA

3 3 1.2 3 ns

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

V

M

V

M

V

M

V

M

tW(L)

1/f

MAX

CPBA or

CPAB

An or Bn

tW(H)

SA00324

t

PHL

t

PLH

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

V

OL

t

PLH

V

OH

An or Bn

An or Bn

V

M

V

M

t

PHL

V

M

V

M

SA00132

Waveform 2. Propagation Delay, Transparent Mode

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

1998 Feb 27

9

AC WAVEFORMS (Continued)

VM = 1.5V, VIN = GND to 3.0V

t

PLH

t

PHL

tW(H)

V

M

V

M

V

M

V

M

V

M

LEAB or

LEBA

An or Bn

V

OH

V

OL

SA00133

Waveform 3. Propagation Delay, Enable to Output, and Enable

Pulse Width

VMV

M

V

M

V

M

V

M

V

M

An
or
Bn

CPAB

or CPBA,

LEAB or LEBA

tS(H) th(H)

t

S

(L)

t

h

(L)

SA00323

Note: The shaded areas indicate when the input is permitted

to change for predictable output performance.

Waveform 4. Data Setup and Hold Times

OEBA

OEAB

An or Bn

V

M

V

M

V

M

t

PZH

t

PHZ

V

OH

V

OH

–0.3V

SA00135

Waveform 5. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

V

OL

OEBA

OEAB

V

M

V

M

t

PZL

t

PLZ

V

M

An or Bn

V

OL

+0.3V

SA00136

Waveform 6. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

TEST CIRCUIT AND WAVEFORMS

PULSE

GENERATOR

R

T

V

IN

D.U.T.

V

OUT

R

L

V

CC

R

L

7.0V

Test Circuit for 3-State Outputs

V

M

V

M

t

W

AMP (V)

NEGATIVE
PULSE

10% 10%

90%

90%

0V

V

M

V

M

t

W

AMP (V)

POSITIVE
PULSE

90% 90%

10%

10%

0V

t

THL

(tF)

t

TLH

(tR)t

THL

(tF)

t

TLH

(tR)

VM = 1.5V

Input Pulse Definition

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.
C

L

= Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

R

T

= Termination resistance should be equal to Z

OUT

of

pulse generators.

INPUT PULSE REQUIREMENTS

FAMILY

Amplitude Rep. Rate t

W

t

R

t

F

74ABT/H16 3.0V 1MHz 500ns 2.5ns 2.5ns

SWITCH POSITION

TEST SWITCH

t

PLZ

closed

t

PZL

closed

All other open

SA00018

C

L

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

1998 Feb 27

10

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

1998 Feb 27

11

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

Philips Semiconductors Product specification

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

yyyy mmm dd

12

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 05-96
Document order number: 9397-750-03493

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

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1] Please consult the most recently issued datasheet before initiating or completing a design.