Datasheet 74ABT16500C Datasheet (Philips)

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INTEGRATED CIRCUITS

74ABT16500C
74ABTH16500C

18-bit universal bus transceiver (3-State)

Product specification
Supersedes data of 1997 Jun 12
IC23 Data Handbook

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1998 Feb 27

Philips Semiconductors Product specification

Quiescent su ly current

18-bit universal bus transceiver (3-State)

FEA TURES

•18-bit bidirectional bus interface

•3-State buffers

•74ABTH16500C incorporates bus-hold data inputs which

eliminate the need for external pull-up resistors to hold unused
inputs

•Output capability: +64mA/-32mA

•TTL input and output switching levels

•Live insertion/extraction permitted

•Power-up reset

•Power-up 3-State

•Negative edge-triggered clock inputs

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

•Flexible operation permits 18 embedded D-type latches or

flip-flops to operate in clocked, transparent, or latched modes.

QUICK REFERENCE DATA

SYMBOL PARAMETER

t

PLH

t

PHL

C
C
I

CCZ

I

CCL

IN

I/O

Propagation delay
An to Bn or Bn to An

Input capacitance (Control pins) VI = 0V or V
I/O pin capacitance Outputs disabled; V

pp

CL = 50pF;
VCC = 5V

Outputs disabled; VCC = 5.5V 500 µA
Outputs low; VCC = 5.5V 8 mA

74ABT16500C

74ABTH16500C

DESCRIPTION

The 74ABT16500C is a high-performance BiCMOS Device which
combines low static and dynamic power dissipation with high speed
and high output drive.

This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA

), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CPAB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA
LEBA and CPBA
active High, and OEBA is active Low).

Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.

Two options are available, 74ABT16500C which does not have the
bus-hold feature and 74ABTH16500C which incorporates the
bus-hold feature.

CONDITIONS

T

= 25°C; GND = 0V

amb

CC

. The output enables are complimentary (OEAB is

TYPICAL UNIT

2.1

1.7
3 pF

= 0V or V

I/O

CC

7 pF

,

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16500C DL BT16500C DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16500C DGG BT16500C DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16500C DL BH16500C DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16500C DGG BH16500C DGG SOT364-1

1998 Feb 27 853-1800 19027

2

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)

LOGIC SYMBOL

3 5 6 8 9 10121314151617192021232426

A0 A1 A2 A3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17A4

OEAB

1

LEAB

2

CPAB

55

OEBA

27

LEBA

28

CPBA

30

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17

54 52 51 49 47 45 44 43 42 41 40 38 37 36 34 33 3148

PIN CONFIGURA TION

74ABT16500C

74ABTH16500C

SA00322

LOGIC SYMBOL (IEEE/IEC)

OEAB

1

LEAB

2

A0

3

GND

4

A1

5

A2

6
7

V

CC

A3

8

A4

9

A5

10
11

GND

A6

12

A7

13

A8

14

A9

15

A10

16

A11

17
18

GND GND

A12

19

A13

20

A14

21
22

V

CC

A15

23

A16

24
25

GND

A17

26
27

OEBA

28 29

LEBA

56

GND
CPAB

55
54

B0

53

GND

52

B1

51

B2

50

V

49

B3

48

B4

47

B5

46

GND

45

B6

44

B7

43

B8

42

B9

41

B10

40

B11
39
38

B12
37

B13
36

B14
35

V
34

B15
33

B16
32

GND
31

B17
30

CPBA

GND

CC

CC

1
55
2

27
30
28

3

5
6
8

9
10
12

13
14
15

16
17
19
20
21
23
24
26

EN1

2C3
C3
G2
EN4

5C6
C6
G5

3D 1 1
416D

54

52
51
49
48

47
45
44
43
42
41
40
38
37
36
34
33
31

1998 Feb 27

SW00035

SH00087

3

Philips Semiconductors Product specification

Disabled, Latch data

Disabled, Clock data

Transparent

Latch data & displa

Clock data & displa

Hold data & displa

18-bit universal bus transceiver (3-State)

74ABTH16500C

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

1 OEAB A-to-B Output enable input

27 OEBA B-to-A Output enable input (active low)

2, 28 LEAB/LEBA A-to-B/B-to-A Latch enable input

55,30 CPAB/CPBA A-to-B/B-to-A Clock input (active falling edge)

3, 5, 6, 8, 9, 10, 12, 13, 14, 15,

16, 17, 19, 20, 21, 23, 24, 26

54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31

4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)

7, 22, 35, 50 V

FUNCTION TABLE

INPUTS

OEAB LEAB CPAB An

L H X X X Z Disabled
L ↓ X h H Z
L ↓ X I L Z
L L H or L X NC Z Disabled, Hold data
L L ↓ h H Z

L L ↓ I L Z
H H X H H H
H H X L L L
H ↓ X h H H
H ↓ X I L L
H L ↓ h H H
H L ↓ I L L
H L H or L X H H
H L H or L X L L

NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level

h = High voltage level one set-up time prior to the Enable or Clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don’t care
Z = High Impedance “off” state
↓ = High-to-Low Enable or Clock transition

A0-A17 Data inputs/outputs (A side)

B0-B17 Data inputs/outputs (B side)

CC

Positive supply voltage

Internal

Registers

OUTPUTS

Bn

OPERATING MODE

74ABT16500C

p

p

y

p

y

p

y

1998 Feb 27

4

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)

LOGIC DIAGRAM

1

OEAB

LEAB

LEBA

OEBA

55

2

28

30

27

CLKAB

CLKBA

74ABT16500C

74ABTH16500C

A1

3

ID

C1

CLK

To 17 other channels

ID
C1

CLK

54

B1

SW00234

1998 Feb 27

5

Philips Semiconductors Product specification

I

DC output current

mA

SYMBOL

UNIT

18-bit universal bus transceiver (3-State)

74ABT16500C

74ABTH16500C

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

V

I
V

I

OK
OUT

OUT

T

CC
IK

stg

DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage

I

DC output diode current VO < 0 –50 mA
DC output voltage

p

Storage temperature range –65 to +150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

3

3

1, 2

–1.2 to +7.0 V

Output in Off or High state –0.5 to +5.5 V

Output in Low state 128

Output in High state –64

RECOMMENDED OPERATING CONDITIONS

PARAMETER LIMITS

MIN MAX

V

CC

V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate; Outputs enabled 10 ns/V

T

amb

DC supply voltage 4.5 5.5 V
Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Input voltage 0.8 V

IL

High-level output current –32 mA
Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

CC

V

1998 Feb 27

6

Philips Semiconductors Product specification

III

t

V

CC

5.5V V

I

GND or

Control pi

011.01.0µA

18-bit universal bus transceiver (3-State)

74ABTH16500C

DC ELECTRICAL CHARACTERISTICS

LIMITS

T

SYMBOL PARAMETER TEST CONDITIONS

MIN TYP MAX MIN MAX

V

V

V

V

RST

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.8 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

OH

VCC = 4.5V; IOH = –32mA; VI = VIL or V

Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

OL

Power-up output voltage

nput leakage curren

3

VCC = 5.5V; IO = 1mA; VI = GND or V
V

= 5.5V; V

= GND or

5.5V

IH

IH

IH

CC

2.5 2.9 2.5 V

3.0 4.0 3.0 V

2.0 2.4 2.0 V

IH

ns 0.

VCC = 4.5V; VI = 0.8V 35 35

I

HOLD

Bus Hold current A and B
Ports6 74ABTH16500C

VCC = 4.5V; VI = 2.0V –75 –75
VCC = 5.5V; VI = 0 to 5.5V ±800

I

OFF

I

PU/PD

IIH + I

IIL + I

I

CEX

I

CCH

I

CCL

I

CCZ

∆I

∆I

I

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V 2 100 100 µA
Power-up/down 3-State

output current
3-State output High current VCC = 5.5V; VO = 5.5V; VI = VIL or V

OZH

3-State output Low current VCC = 5.5V; VO = 0.0V; VI = VIL or V

OZL

4

Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V

O

Output current

1

VCC = 2.1V; VO = 0.0V or VCC;
VOE = Don’t care

IH

IH

CC

VCC = 5.5V; VO = 2.5V –50 –80 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or

V

CC

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

CC

VCC = 5.5V; Outputs 3–State;

Additional supply current
per input pin

CC

74ABT16500C
Additional supply current

per input pin

CC

74ABTH16500C

VI = GND or V

2

2

VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND

VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V .

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V
transition time of up to 100µsec is permitted.

5. Unused pins at V

6. This is the bus hold overdrive current required to force the input to the opposite logic state.

or GND.

CC

between 0V and 2.1V , with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a

CC

= +25°C

amb

0.35 0.55 0.55 V

0.13 0.55 0.55 V

2 50 50 µA

1.0 10 10 µA

–1.0 –10 –10 µA

2 50 50 µA

0.5 2 2 mA

8 19 19 mA

0.5 2 2 mA

5.0 50 50 µA

200 500 500 µA

74ABT16500C

T

= –40°C

amb

to +85°C

UNIT

µA

1998 Feb 27

7

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

f

max

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

ts(H)
ts(L)

th(H)
th(L)

ts(H)
t

(L)

s

th(H)
th(L)

t

w

tw(H)

Maximum clock frequency 1 150 225 150 MHz
Propagation delay

An to Bn or Bn to An
Propagation delay

LEAB to Bn or LEBA to An
Propagation delay

CPAB to Bn or CPBA to An
Output enable time

to HIGH and LOW level
Output disable time

from HIGH and LOW level

Setup time, HIGH or LOW
An to CPAB or Bn to CPBA

Hold time, HIGH or LOW
An to CPAB or Bn to CPBA

Setup time, HIGH or LOW
An to LEAB or Bn to LEBA

Hold time HIGH or LOW
An to LEAB or Bn to LEBA

Pulse width, HIGH or LOW
CPAB or CPBA

Pulse width, HIGH
LEAB or LEBA

2

3

1
5

6
5

6

4

4

4

4

1 3 1.2 3 ns

3 3 1.2 3 ns

74ABT16500C

74ABTH16500C

LIMITS

T

= +25oC

amb

VCC = +5.0V

MIN TYP MAX MIN MAX

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.5

1.5

1.4

T

2.1

1.7

3.2

2.8

3.4

2.6

3.3

2.4

3.3

2.5

amb

V

= +25oC

= +5.0V

CC

3.0

2.5

4.3

3.7

4.5

3.5

4.4

3.2

4.3

3.3

MIN TYP MIN

2.0

2.0

0.7

0.7

2.0

2.0

0.7

0.7

0.7

0.6

–0.5
–0.8

0.1

0.1

–0.1
–0.1

T

amb

VCC = +5.0V ±0.5V

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.5

1.5

1.4

LIMITS

T

amb

V

CC

= –40 to +85oC

3.4

3.0

4.9

4.0

5.3

4.6

5.0

3.9

5.3

3.9

= –40 to +85oC

= +5.0V ±0.5V

2.0

2.0

0.7

0.7

2.0

2.0

0.7

0.7

UNIT

ns

ns

ns

ns

ns

UNIT

ns

ns

ns

ns

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

1/f

MAX

V

CPBA or

CPAB

An or Bn

M

t

tW(L)

PHL

tW(H)

V

M

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

1998 Feb 27

V

M

t

PLH

V

M

SA00324

An or Bn

An or Bn

V

M

t

PLH

V

M

t

PHL

V

OH

V

M

V

M

V

OL

SA00132

Waveform 2. Propagation Delay, Transparent Mode

8

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)

AC WAVEFORMS (Continued)

VM = 1.5V, VIN = GND to 3.0V

LEAB or

LEBA

An or Bn

V

M

tW(H)

t

PHL

V

M

V

M

Waveform 3. Propagation Delay, Enable to Output, and Enable

Pulse Width

An
or
Bn

CPAB

or CPBA,

LEAB or LEBA

Note: The shaded areas indicate when the input is permitted

to change for predictable output performance.

VMV

M

tS(H) th(H)

V

M

Waveform 4. Data Setup and Hold Times

V

M

t

PLH

V

OH

V

M

V

OL

SA00133

V

V

M

M

(L)

V

M

t

h

SA00323

t

(L)

S

74ABT16500C

74ABTH16500C

OEBA

V

M

OEAB

t

PZH

V

An or Bn

M

Waveform 5. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

OEBA

V

OEAB

An or Bn

M

t

PZL

V

M

Waveform 6. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

V

M

t

PHZ

V

M

t

PLZ

V

V

OH

V

–0.3V

OH

SA00135

+0.3V

OL

V

SA00136

OL

TEST CIRCUIT AND WAVEFORMS

V

CC

PULSE

GENERATOR

V

IN

R

D.U.T.

T

V

OUT

C

L

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t

PLZ

t

PZL

closed
closed

All other open

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

t

90%

7.0V
NEGATIVE

R

L

R

L

PULSE

POSITIVE
PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

W

V

M

(tF)

(tR)t

V

M

t

W

90%

10%

t

TLH

THL

AMP (V)

0V

(tR)

(tF)

AMP (V)

0V

VM = 1.5V

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

of

Amplitude Rep. Rate t

74ABT/H16 3.0V 1MHz 500ns 2.5ns 2.5ns

t

W

t

R

F

SA00018

1998 Feb 27

9

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)

74ABT16500C

74ABTH16500C

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

1998 Feb 27

10

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)

74ABT16500C

74ABTH16500C

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

1998 Feb 27

11

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74ABT16500C

74ABTH16500C

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 05-96
Document order number: 9397-750-03493

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