Datasheet 74ABT16373CMTD, 74ABT16373CSSCX, 74ABT16373CSSC, 74ABT16373CMTDX Datasheet (Fairchild Semiconductor)
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© 1999 Fairchild Semiconductor Corporation DS011666 www.fairchildsemi.com
March 1994
Revised November 1999
74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs
74ABT16373
16-Bit Transparent D-Type Latch with 3-STATE Outputs
General Description
The ABT16373 cont ains sixteen n on-inverti ng latches with
3-STAT E outputs and is intende d for bus oriented app lications. The device is byte controlled. T he flip-flops appe ar
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE
) is LOW. When OE is HIGH, the outputs are in
high Z state.
Features
■ Separate control logic for each byte
■ 16-bit version of the ABT373
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
■ Guaranteed latch-up protection
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Order Number Package Number Package Description
74ABT16373CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16373CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enabl e Input
D
0–D15
Data Inputs
O
0–O15
Outputs
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74ABT16373
Functional Description
The ABT16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obt ain full
16-bit operation. The following description applies to each
byte. When the Latch E nable (LE
n
) input is HIGH, data on
the D
n
enters the latches. In this condition the la tches are
transparent, i.e., a latch output will change states each time
its D input changes. When LE
n
is LOW, the latches store
information that was prese nt on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE
n
. The 3-
STATE standard outputs are controlled by the Output
Enable (OE
n
) input. When OEn is LOW, the standard out-
puts are in the 2-state mode. When OE
n
is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Tr uth Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Previous = previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
Inputs Outputs
LE
1
OE
1
D0–D
7
O0–O
7
XH X Z
HL L L
HL H H
L L X (Previous)
Inputs Outputs
LE
2
OE
2
D8–D
15
O8–O
15
XH X Z
HL L L
HL H H
LL X (Previous)
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74ABT16373
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired . Functional operation
under these conditions is not implied.
Note 2: Either voltage lim it or c urrent limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed, but not tested.
Note 4: For 8 bits toggling, I
CCD
< 0.8 mA/MHz.
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State −0.5V to +5.5V
in the HIGH State −0.5V to V
CC
Current Applied to Output
in LOW State (Max) twice therated I
OL
(mA)
DC Latchup Source Current: OE
Pin
−350 mA
(Across Comm Operating Range)
Other Pins −500 mA
Over Voltage Latchup (I/O) 10V
Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH Voltage 2.5
Min
IOH = −3 mA
2.0 IOH = −32 mA
V
OL
Output LOW Voltage 0.55 V Min IOL = 64 mA
I
IH
Input HIGH Current 1
µAMax
VIN = 2.7V (Note 3)
1V
IN
= V
CC
I
BVI
Input HIGH Current Breakdown Test 7 µAMaxVIN = 7.0V
I
IL
Input LOW Current −1
µAMax
VIN = 0.5V (Note 3)
−1V
IN
= 0.0V
V
ID
Input Leakage Test 4.75 V 0.0 IID = 1.9 µA
All Other Pins Grounded
I
OZH
Output Leakage Current 10 µA0 − 5.5V
V
OUT
= 2.7V; OE = 2.0V
I
OZL
Output Leakage Current −10 µA0 − 5.5V
V
OUT
= 0.5V; OE = 2.0V
I
OS
Output Short-Circuit Current −100 −275 mA Max V
OUT
= 0.0V
I
CEX
Output HIGH Leakage Current 50 µAMaxV
OUT
= V
CC
I
ZZ
Bus Drainage Test 100 µA0.0V
OUT
= 5.5V; All Others GND
I
CCH
Power Supply Current 2.0 mA Max All Outputs HIGH
I
CCL
Power Supply Current 62 mA Max All Outputs LOW
I
CCZ
Power Supply Current
2.0 mA Max
OE = V
CC
All Others at VCC or GND
I
CCT
Additional ICC/Input Outputs Enabled 2.5 mA VI = VCC − 2.1V
Outputs 3-STATE 2.5 mA Max Enable Input VI = VCC − 2.1V
Outputs 3-STATE 2.5 mA Data Input VI = VCC − 2.1V
All Others at VCC or GND
I
CCD
Dynamic I
CC
No Load mA/
Max
Outputs Open, LE = V
CC
(Note 3) 0.15
MHz
OE = GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
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74ABT16373
AC Electrical Characteristics
(SOIC and SSOP Packages)
AC Operating Requirements
(SOIC and SSOP Packages)
Capacitance
Note 5: C
OUT
is measured at frequency f = 1 MHz, per MIL-STD-883, Me th od 3012.
Symbol Parameter
TA = +25°CT
A
= −40°C to +85°C
Units
V
CC
= +5.0V VCC = 4.5V to 5.5V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay 1.4 5.6 1.4 5.6
ns
t
PHL
Dn to O
n
1.4 5.6 1.4 5.6
t
PLH
Propagation Delay 1.7 6.0 1.7 6.0
ns
t
PHL
LE to O
n
1.7 5.5 1.7 5.5
t
PZH
Output Enable Time 1.1 6.1 1.1 6.1
ns
t
PZL
1.5 5.6 1.5 5.6
t
PHZ
Output Disable Time 2.4 7.1 2.4 7.1
ns
t
PLZ
1.6 6.5 1.6 6.5
Symbol Parameter
T
A
= +25°CT
A
= −40°C to +85°C
Units
V
CC
= +5.0V VCC = 4.5V to 5.5V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
f
TOGGLE
Maximum Toggle Frequency 100 MHz
tS(H) Setup Time, HIGH 1.5 1.5
ns
tS(L) or LOW Dn to LE 1.5 1.5
tH(H) Hold Time, HIGH 1.0 1.0
ns
tH(L) or LOW Dn to LE 1.0 1.0
tW(H) Pulse Width,
3.0 3.0 ns
LE HIGH
Symbol Parameter Typ Units
Conditions
(TA = 25°C)
C
IN
Input Capacitance 5 pF VCC = 0V
C
OUT
(Note 5) Output Capacitance 11 pF VCC = 5.0V
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74ABT16373
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Num b er MS48A
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74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical com ponent in any compon ent of a l ife supp ort
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