Datasheet 74ABTH16373BDL, 74ABTH16373BDGG, 74ABT16373BDL, 74ABT16373BDGG Datasheet (Philips)
Page 1
INTEGRATED CIRCUITS
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
Product specification
Supersedes data of 1995 Aug 03
IC23 Data Handbook
1998 Feb 27
Page 2
Philips Semiconductors Product specification
Quiescent su ly current
16-bit transparent latch (3-State)
FEA TURES
•16-bit transparent latch
•Multiple V
•Power-up 3-State
•Live insertion/extraction permitted
•Power-up reset
•3-State output buffers
•74ABTH16373B incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
•Output capability: +64mA/–32mA
•I
CCL
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE
The data on each set of D inputs are transferred to the latch outputs
when the Latch Enable (nE) input is High. The latch remains
transparent to the data inputs while nE is High, and stores the data
that is present one setup time before the High-to-Low enable
transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-Low Output Enable (nOE
independent of the latch operation.
and GND pins minimize switching noise
CC
–19 mA maximum
) control gates.
) controls eight 3-State buffers
74ABT16373B
74ABTH16373B
When nOE
outputs. When nOE
“OFF” state, which means they will neither drive nor load the bus.
Two options are available, 74ABT16373B which does not have the
bus-hold feature and 74ABTH16373B which incorporates the
bus-hold feature.
PIN CONFIGURATION
is Low, the latched or transparent data appears at the
is High, the outputs are in the High-impedance
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
V
2Q4
2Q5
GND
2Q6
2Q7
2OE
1
2
3
4
5
6
7
CC
8
9
10
11
12
13
14
15
16
17
18
CC
19
20
21
22
23
24
48
1E
47
1D0
1D1
46
GND
45
1D2
44
43
1D3
42
V
41
1D4
1D5
40
GND
39
1D6
38
1D7
37
2D0
36
2D1
35
GND
34
33
2D2
2D3
32
31
V
2D4
30
29
2D5
28
GND
27
2D6
26
2D7
25
2E
SA00379
CC
CC
QUICK REFERENCE DA TA
SYMBOL PARAMETER
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
I
CCL
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin SSOP type III –40°C to +85°C 74ABT16373B DL BT16373B DL SOT370-1
48-Pin TSSOP type II –40°C to +85°C 74ABT16373B DGG BT16373B DGG SOT362-1
48-Pin SSOP type III –40°C to +85°C 74ABTH16373B DL BH16373B DL SOT370-1
48-Pin TSSOP type II –40°C to +85°C 74ABTH16373B DGG BH16373B DGG SOT362-1
1998 Feb 27 853-1751 19027
CONDITIONS
T
= 25°C; GND = 0V
amb
Propagation delay
Dn to Qn
CL = 50pF; VCC = 5V
Input capacitance VI = 0V or V
CC
TYPICAL UNIT
2.5
2.0
ns
4 pF
Output capacitance VO = 0V or VCC; 3-State 7 pF
pp
Outputs disabled; VCC = 5.5V 500 µA
Outputs low; VCC = 5.5V 8 mA
2
Page 3
Philips Semiconductors Product specification
16-bit transparent latch (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
47, 46, 44, 43, 41, 40,
38, 37, 36, 35, 33, 32,
30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12,
13, 14, 16, 17, 19, 20,
22, 23
1, 24 1OE, 2OE
48, 25 1E, 2E
4, 10, 15, 21, 28, 34,
39, 45
7, 18, 31, 42 V
LOGIC SYMBOL
48
1
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
GND Ground (0V)
47 46 44 43
1D0 1D1 1D2 1D3
1LE
1OE
1Q0 1Q1 1Q2651Q3
CC
41 40 38 37
1D4 1D5 1D6 1D7
1Q4 1Q5 1Q6
Data inputs
Data outputs
Output enable inputs
(active-Low)
Enable inputs
(active-High)
Positive supply
voltage
1Q7
LOGIC SYMBOL (IEEE/IEC)
1OE
1E
2OE
2E
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C3
2EN
C4
3D
4D
74ABT16373B
74ABTH16373B
1 ∇
2 ∇
SA00380
2
1Q0
3
1Q1
5
1Q2
6
1Q3
8
1Q4
9
1Q5
11
1Q6
12
1Q7
13
2Q0
14
2Q1
16
2Q2
17
2Q3
19
2Q4
20
2Q5
22
2Q6
23
2Q7
36 35 33 32
25
24
2D02D212D2 2D3
2LE
2OE
2Q0 2Q1 2Q2 2Q3
LOGIC DIAGRAM
nD0
nLE
32
1413 1716
D
E Q
98
30 29 27 26
2D4 2D5 2D6 2D7
2Q4 2Q5 2Q6 2Q7
2019 2322
SA00044
nD1
D
EQ
1211
nD2
D
EQ
nD3
D
EQ
nD4
D
EQ
nD5
D
EQ
nD6
D
EQ
nD7
D
EQ
nOE
1998 Feb 27
nQ0
nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
SA00046
3
Page 4
Philips Semiconductors Product specification
OPERATING MODE
I
DC output current
mA
SYMBOL
PARAMETER
UNIT
16-bit transparent latch (3-State)
74ABT16373B
74ABTH16373B
FUNCTION TABLE
INPUTS
nOE nE nDx
L
L
L
L
H
H
↓
↓
L
H
i
h
INTERNAL
REGISTER
L
H
L
H
L L X NC NC Hold
H
H
L
H
X
Dn
NC
Dn
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low E transition
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
OUT
T
stg
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
p
Storage temperature range –65 to 150 °C
PARAMETER CONDITIONS RATING UNIT
3
3
1, 2
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
OUTPUTS
nQ0 – nQ7
L
H
L
H
Z
Z
Enable and read register
Latch and read register
Disable outputs
–1.2 to +7.0 V
output in Off or High state –0.5 to +5.5 V
output in Low state 128
output in High state –64
RECOMMENDED OPERATING CONDITIONS
1998 Feb 27
LIMITS
MIN MAX
V
CC
V
V
V
I
OH
I
OL
DC supply voltage 4.5 5.5 V
Input voltage 0 V
I
High-level input voltage 2.0 V
IH
Low-level Input voltage 0.8 V
IL
High-level output current –32 mA
Low-level output current 64 mA
CC
V
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
4
Page 5
Philips Semiconductors Product specification
I
g
V
V
V
GND
±0.01±1±1µA
74ABTH16373B
Data pins
5
6
74ABTH16373B
16-bit transparent latch (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
SYMBOL PARAMETER TEST CONDITIONS
MIN TYP MAX MIN MAX
V
V
V
V
RST
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
IK
VCC = 4.5V; IOH = –3mA; VI = VIL or V
High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V
OH
VCC = 4.5V; IOH = –32mA; VI = VIL or V
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
OL
Power-up output voltage
Input leakage current
I
74ABT16373B
3
VCC = 5.5V; IO = 1mA; VI = GND or V
;
= 5.5V;
CC
=
I
CC
or
IH
IH
IH
IH
CC
VCC = 5.5V; VI = VCC or GND Control pins ±0.01 ±1 ±1 µA
Input leakage current
I
I
VCC = 5.5V; VI = V
VCC = 5.5V; VI = 0
CC
p
VCC = 4.5V; VI = 0.8V 50 50
I
HOLD
Bus Hold current A inputs
VCC = 4.5V; VI = 2.0V –75 –75
VCC = 5.5V; VI = 0 to 5.5V ±800
I
OFF
IPU/I
I
OZH
I
OZL
I
CEX
I
CCH
I
CCL
I
CCZ
∆I
∆I
Power-off leakage current VCC = 0.0V; VO or V
Power-up/down 3-State
PD
output current
4
VCC = 2.1V; VO = 0.5V; VI = GND or VCC;
VOE = GND
3-State output High current VCC = 5.5V; VO = 5.5V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.0V; VI = VIL or V
I
O
Output current
Output High leakage
current
1
VCC = 5.5V; VO = 2.5V –50 –70 –180 –50 –180 mA
VCC = 5.5V; VO = 5.5V; VI = GND or V
VCC = 5.5V; Outputs High, VI = GND or V
Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V
VCC = 5.5V; Outputs 3-State;
VI = GND or V
Additional supply current
per input pin
CC
74ABT16373B
Additional supply current
per input pin
CC
74ABTH16373B
2
2
VCC = 5.5V; one input at 3.4V, other inputs
at VCC or GND
VCC = 5.5V; one input at 3.4V, other inputs
at VCC or GND
≤
4.5V ±5.0 ±100 ±100 µA
I
IH
IH
CC
CC
CC
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V .
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
transition time of up to 100µsec is permitted.
5. Unused pins at V
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
or GND.
CC
between 0V and 2.1V , with a transition time of up to 10msec. From VCC = 2.1 to VCC = 5V ± 10% a
CC
= +25°C
amb
2.5 2.9 2.5 V
3.0 3.4 3.0 V
2.0 2.4 2.0 V
0.42 0.55 0.55 V
0.13 0.55 0.55 V
0.01 1 1 µA
–1 –3 –5 µA
±5.0 ±50 ±50 µA
0.5 10 10 µA
–0.5 –10 –10 µA
0.1 50 50 µA
0.5 2 2 mA
8 19 19 mA
0.5 2 2 mA
5 100 100 µA
0.5 1.5 1.5 mA
74ABT16373B
74ABTH16373B
T
= –40°C
amb
to +85°C
UNIT
µA
1998 Feb 27
5
Page 6
Philips Semiconductors Product specification
16-bit transparent latch (3-State)
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL PARAMETER WAVEFORM
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL PARAMETER WAVEFORM
ts(H)
ts(L)
th(H)
th(L)
tw(H)
Propagation delay
nDx to nQx
Propagation delay
nE to nQx
Output enable time
to High and Low level
Output disable time
from High and Low level
Setup time, High or Low
nDx to nE
Hold time, High or Low
nDx to nE
Enable pulse width
High
2
1
4
5
4
5
3
3
1 2.5 1.0 2.5 ns
74ABT16373B
74ABTH16373B
LIMITS
T
= +25°C
amb
VCC = +5.0V
MIN TYP MAX MIN MAX
1.5
1.1
1.6
1.3
1.2
1.3
1.9
1.7
2.5
2.0
2.5
2.1
2.3
2.3
3.1
2.6
3.8
3.1
3.8
3.1
3.5
3.5
4.5
3.8
LIMITS
T
= +25°C
amb
VCC = +5.0V
MIN TYP MIN
1.0
1.0
0.5
0.5
0.0
0.3
–0.2
0.0
T
= –40 to +85°C
amb
VCC = +5.0V ±0.5V
1.5
1.1
1.6
1.3
1.2
1.3
1.9
1.7
T
= –40 to +85°C
amb
VCC = +5.0V ±0.5V
4.4
3.8
4.4
3.6
4.6
4.5
5.3
4.2
1.0
1.0
0.5
0.5
UNIT
ns
ns
ns
ns
UNIT
ns
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
nE
nQx
V
M
tw(H)
t
PHL
Waveform 1. Propagation Delay, Enable to Output, and
V
M
V
M
Enable Pulse Width
V
M
t
PLH
V
M
SA00047
nDx
nQx
V
M
t
PLH
V
M
t
PHL
V
M
V
M
SA00048
Waveform 2. Propagation Delay for Data to Outputs
1998 Feb 27
6
Page 7
Philips Semiconductors Product specification
ÉÉÉ
ÉÉÉ
16-bit transparent latch (3-State)
V
nDx
nE
V
M
M
t
(H)
s
NOTE: The shaded areas indicate when the input is per-
mitted to change for predictable output performance.
(H)
t
h
V
M
Waveform 3. Data Setup and Hold Times
nOE
nQx
V
M
t
PZH
V
M
V
M
V
V
M
M
t
(L)
s
V
M
SA00049
t
PHZ
V
OH
VOH – 0.3V
74ABT16373B
74ABTH16373B
nOE
(L)
t
h
nQx
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
0V
V
M
t
PZL
V
M
t
PLZ
V
M
VOL + 0.3V
V
OL
SA00051
SA00050
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
TEST CIRCUIT AND WAVEFORM
V
CC
R
PULSE
GENERATOR
V
IN
R
D.U.T.
T
V
OUT
C
L
L
R
L
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
t
W
(tF)
(tR)t
t
W
90%
V
M
t
TLH
THL
V
M
10%
7.0V
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
V
M
10% 10%
t
THL
t
TLH
90% 90%
V
M
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude Rep. Rate t
t
W
R
74ABT/H16 3.0V 1MHz 500ns 2.5ns 2.5ns
AMP (V)
0V
(tR)
(tF)
AMP (V)
0V
t
F
SA00018
1998 Feb 27
7
Page 8
Philips Semiconductors Product specification
16-bit transparent latch (3-State)
74ABT16373B
74ABTH16373B
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
1998 Feb 27
8
Page 9
Philips Semiconductors Product specification
16-bit transparent latch (3-State)
74ABT16373B
74ABTH16373B
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1
1998 Feb 27
9
Page 10
Philips Semiconductors Product specification
16-bit transparent latch (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74ABT16373B
74ABTH16373B
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-03491
yyyy mmm dd
10
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