Datasheet 74ABT162244MTDX, 74ABT162244CSSX, 74ABT162244CSSC, 74ABT162244CMTD Datasheet (Fairchild Semiconductor)

74ABT162244
16-Bit Buffer/Line Driver with

25Ω Series Resistors in the Outputs

74ABT162244 16-Bit Buffer/Line Driver with 25Ω Series Resist ors in the Outputs

April 1992
Revised November 1999

General Description

The ABT162244 contains sixteen non-inverting buffers with
3-STATE outputs designed to be employ ed as a memory
and address driver, clock driver, or bus oriented transmit­ter/receiver. The device is nibble cont rolled. Individual 3­STATE control inputs can be shorte d together for 8-bit or
16-bit operation.

The 25Ω series resist ors in the outputs re duce r inging a nd
eliminate the need for external resistors.

Features

■ Separate control logic for each nibble

■ 16-bit version of the ABT2244

■ Guaranteed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

Ordering Code:

Order Number Package Number Package Description

74ABT162244CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT162244CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the or dering code.

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names Description

OE

n

I

0–I15

O

0–O15

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Output Enable Input (Active LOW)
Inputs
Outputs

Truth Tables

Inputs Outputs

OE

1

74ABT162244

LL L
LH H
HX Z

Inputs Outputs

OE

3

LL L
LH H
HX Z

Inputs Outputs

OE

2

LL L
LH H
HX Z

Inputs Outputs

OE

4

LL L
LH H
HX Z

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

I0–I

I8–I

I4–I

I12–I

Logic Diagram

3

11

7

15

O0–O

O8–O

O4–O

O12–O

3

11

7

15

Schematic of each Output

Functional Description

The ABT162244 contains sixteen non-inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble funct ioning ide ntically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation.

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Absolute Maximum Ratings(Note 1) Recommended Operating

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

Pin Potential to Ground Pin −0.5V to +7.0V

CC

Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disabled or
Power-Off State −0.5V to 5.5V
in the HIGH State −0.5V to V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

DC Latchup Source Current −500 mA
Over Voltage Latchup (I/O) 10V

Conditions

Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns

CC

Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired . Functional operation

(mA)

under these conditions is not implied.

Note 2: Either voltage lim it or c urrent limit is sufficient to protect inputs.

DC Electrical Characteristics

74ABT162244

Symbol Parameter Min Typ Max Units

V
V
V
V

Input HIGH Voltage 2.0 V Recognized HIGH Signal

IH

Input LOW Voltage 0.8 V Recognized LOW Signal

IL

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

CD

Output HIGH Voltage 2.5 V Min IOH = −3 mA

OH

2.0 V Min IOH = −32 mA
V
I

Output LOW Voltage 0.8 V Min IOL = 12 mA

OL

Input HIGH Current 1

IH

1V
I
I

Input HIGH Current Breakdown Test 7 µAMaxVIN = 7.0V

BVI

Input LOW Current −1

IL

−1V

V

I
I

I
I
I
I
I
I

I

Input Leakage T est 4.75 V 0.0 IID = 1.9 µA

ID

Output Leakage Current 10 µA0 − 5.5V

OZH

Output Leakage Current −10 µA0 − 5.5V

OZL

Output Short-Circuit Current −100 −275 mA Max V

OS

Output High Leakage Current 50 µAMaxV

CEX

Bus Drainage Test 100 µA0.0V

ZZ

Power Supply Current 2.0 mA Max All Outputs HIGH

CCH

Power Supply Current 60 mA Max All Outputs LOW

CCL

Power Supply Current

CCZ

Additional ICC/Input Outputs Enabled 3.0 mA VI = VCC − 2.1V

CCT

2.0 mA Max

Outputs 3-STATE 3.0 mA Max Enable Input VI = VCC − 2.1V
Outputs 3-STATE 50 µA Data Input VI = VCC − 2.1V

I

CCD

Dynamic I

CC

No Load mA/

(Note 3) 0.1

Note 3: Guaranteed, but not tested.

MHz

V

CC

µAMax

µAMax

VIN = 2.7V (Note 3)

VIN = 0.5V (Note 3)

All Other Pins Grounded
V
V

OEn = V
All Others at VCC or GND

All Others at VCC or GND
Outputs OPEN

Max

OEn = GND
One Bit Toggling, 50% Duty Cycle

Conditions

= V

IN

CC

= 0.0V

IN

= 2.7V; OEn = 2.0V

OUT

= 0.5V; OEn = 2.0V

OUT

= 0.0V

OUT

= V

OUT

CC

= 5.5V; All Others GND

OUT

CC

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AC Electrical Characteristics

= +25°CT

T

A

V

= +5V VCC = 4.5V–5.5V

Symbol Parameter

74ABT162244

t
t
t
t
t
t

PLH
PHL
PZH
PZL
PHZ
PLZ

Propagation 1.0 2.4 3.9 1.0 3.9
Delay Data to Outputs 1.0 3.2 4.7 1.0 4.7
Output 1.5 3.5 6.3 1.5 6.3
Enable Time 1.5 4.2 6.9 1.5 6.9
Output 1.0 4.2 6.7 1.0 6.7
Disable Time 1.0 3.8 6.7 1.0 6.7

Min Typ Max Min Max

CC

= 50 pF CL = 50 pF

C

L

Capacitance

Symbol Parameter Typ Units

C

IN

C

(Note 4) Output Capacitance 9.0 pF VCC = 5.0V

OUT

Note 4: C

Input Capacitance 5.0 pF VCC = 0.0V

is measured at frequency f = 1 MHz per MIL-STD-883, Me t hod 3012.

OUT

= −40°C to +85°C

A

Conditions

T

A

Units

ns

ns

ns

= 25°C

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AC Loading

*Includes jig and probe capacitance

FIGURE 1. Standard AC Test Load

AC Waveforms

FIGURE 2. Input Pulse Requirements

Amplitude Rep. Rate t

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

FIGURE 3. Test Input Signal Requirements

W

t

r

74ABT162244

t

f

FIGURE 4. Propagation Delay Waveforms for Inverting

and Non-Inverting Functions

FIGURE 5. Propagation Delay,

Pulse Width Waveforms

FIGURE 6. 3-STAT E Outp ut HIGH

and LOW Enable and Disable Times

FIGURE 7. Setup Time, Hold Time

and Recovery Time Waveforms

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Physical Dimensions inches (millimeters) unless otherwise noted

74ABT162244

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

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Package Number MS48A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74ABT162244 16-Bit Buffer/Line Driver with 25Ω Series Resist ors in the Outputs

48-Lead Thin Shrin k Small Ou tlin e Pack age (TSSOP), JEDEC MO-153, 6.1mm Wide

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the l abe ling, can be rea­sonably expected to result in a significant injury to the
user.

Package Number MTD48

2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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