Datasheet 74ABT10PW, 74ABT10N, 74ABT10DB, 74ABT10D Datasheet (Philips)

Page 1
INTEGRATED CIRCUITS
74ABT10
Triple 3-input NAND gate
Product specification 1995 Sep 22 IC23 Data Handbook
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Page 2
Philips Semiconductors Product specification
CC
QUICK REFERENCE DATA
CONDITIONS
SYMBOL PARAMETER
T
Propagation
IN
CC
delay An, Bn, Cn to Y
n
Output to Output skew
Input capacitance
Total supply current
CL = 50pF; VCC = 5V
VI = 0V or V Outputs disabled;
VCC = 5.5V
t
PLH
t
PHL
t
OSLH
t
OSHL
C
I
PIN CONFIGURATION
1
A0
2
B0 A1
3
B1
4
C1
5
1
6
Y
GND
PIN DESCRIPTION
PIN
NUMBER
1, 2, 3, 4, 5,
9, 10, 11, 13
6, 8, 12 Yn Data outputs
7 GND Ground (0V)
14 V
SYMBOL NAME AND FUNCTION
An, Bn,
Cn
Data inputs
Positive supply voltage
CC
LOGIC DIAGRAM
1
A0
2
B0
13
C0
3
A1
4
B1
5
C1
9
A2
10
B2
11
VCC = Pin 14 GND = Pin 7
C2
= 25°C;
amb
GND = 0V
SA00346
CC
14
V
13
C0
12
Y
11
C2 B2
10
A2
9 87
Y2
12
6
8
SA00348
TYPICAL UNIT
3.3
2.2
0.4 ns
3 pF
50 µA
CC
0
Y0
Y1
Y2
ns
LOGIC SYMBOL
1 2 13 3 4 5 9 10
A0 B0 C0 B1 C1 A2 B2A1
Y0Y1Y2
VCC = Pin 14 GND = Pin 7
12 6 8
LOGIC SYMBOL (IEEE/IEC)
1
2
13
3
4
5
9
10
11
&
FUNCTION TABLE
INPUTS OUTPUTS
An Bn Cn Yn
L L L H L L H H L H L H
L H H H H L L H H L H H H H L H H H H L
NOTES:
H = High voltage level L = Low voltage level
11
C2
SA00347
12
6
8
SV00059
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
14-Pin Plastic DIP –40°C to +85°C 74ABT10 N 74ABT10 N SOT27-1 14-Pin plastic SO –40°C to +85°C 74ABT10 D 74ABT10 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +85°C 74ABT10 DB 74ABT10 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT10 PW 74ABT10PW DH SOT402-1
1995 Sep 22 853-1810 15793
2
Page 3
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
74ABT10Triple 3-input NAND gate
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL PARAMETER CONDITIONS RATING UNIT
V
I
V
CC
I
IK
V
I
OK
OUT
OUT
T
stg
DC supply voltage –0.5 to +7.0 V DC input diode current VI < 0 –18 mA
I
DC input voltage
3
–1.2 to +7.0 V DC output diode current VO < 0 –50 mA DC output voltage
3
output in Off or High state –0.5 to +5.5 V DC output current output in Low state 40 mA Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
V
CC
V V V I
OH
I
OL
t/v Input transition rise or fall rate 0 10 ns/V
T
amb
DC supply voltage 4.5 5.5 V Input voltage 0 V
I
High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
High-level output current –15 mA Low-level output current 20 mA
Operating free-air temperature range –40 +85 °C
CC
V
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
V
V
V
I
OFF
I
CEX
I
I
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
IK
High-level output voltage VCC = 4.5V; IOH = –15mA; VI = VIL or V
OH
Low-level output voltage VCC = 4.5V; IOL = 20mA; VI = VIL or V
OL
I
Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
I
IH
IH
Power-off leakage current VCC = 0.0V; VO or VI 4.5V ±5.0 ±100 ±100 µA Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
I
Output current
O
Quiescent supply current VCC = 5.5V; VI = GND or V
CC
Additional supply current per
CC
input pin
1
2
VCC = 5.5V; VO = 2.5V –50 –75 –180 –50 –180 mA
VCC = 5.5V; One data input at 3.4V, other inputs at VCC or GND
CC
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flop or latch after applying the power.
T
= +25°C
amb
MIN TYP MAX MIN MAX
2.5 2.9 2.5 V
0.35 0.5 0.5 V
5.0 50 50 µA
2 50 50 µA
0.25 500 500 µA
T
amb
to +85°C
= –40°C
UNIT
1995 Sep 22
3
Page 4
Philips Semiconductors Product specification
74ABT10Triple 3-input NAND gate
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500
LIMITS
T
= +25°C
SYMBOL PARAMETER
WAVEFORM
amb
VCC = +5.0V
MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
OSHL
t
OSLH
Propagation delay An, Bn, Cn to Yn
Output to Output skew
1
An or Bn to Yn
1
1.0
1.0
3.3
2.2
2 0.4 0.5 0.5 ns
NOTE:
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the the same direction, either HIGH–to-LOW (t parameter guaranteed by design.
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
4.7
3.3
T
= –40°C to +85°C
amb
VCC = +5.0V ±0.5V
1.0
1.0
) or LOW-to-HIGH (t
OSHL
5.3
3.7
UNIT
ns
OSLH
);
An, Bn, Cn
Yn
V
M
t
PHL
V
M
t
PLH
V
M
V
M
Waveform 1. Propagation Delay for Inverting Outputs
TEST CIRCUIT AND WAVEFORMS
V
CC
PULSE
GENERATOR
V
IN
R
D.U.T.
T
Test Circuit for Outputs
V
OUT
C
L
SA00357
R
L
INPUT
OUTPUT
OUTPUT N same part
90%
NEGATIVE PULSE
POSITIVE PULSE
10%
t
PHL
MIN
t
PLH
MIN
t
PLH
MAX
t
OSLH
t
PHL
Waveform 2. Common edge skew
t
W
V
M
10% 10%
(tF)
t
THL
t
(tR)t
TLH
90% 90%
V
M
t
W
90%
V
M
V
M
10%
VM = 1.5V
MAX
t
OSHL
t
TLH
THL
SA00381
AMP (V)
0V
(tR)
(tF)
AMP (V)
0V
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. C
= Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
1995 Sep 22
OUT
of
FAMILY
74ABT
4
Input Pulse Definition
INPUT PULSE REQUIREMENTS
Amplitude Rep. Rate t
W
3.0V 1MHz 500ns 2.5ns
t
t
R
F
2.5ns
SH00067
Page 5
Philips Semiconductors Product specification
74ABT10Triple 3-input NAND gate
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
1995 Sep 22
5
Page 6
Philips Semiconductors Product specification
74ABT10Triple 3-input NAND gate
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
1995 Sep 22
6
Page 7
Philips Semiconductors Product specification
74ABT10Triple 3-input NAND gate
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
1995 Sep 22
7
Page 8
Philips Semiconductors Product specification
74ABT10Triple 3-input NAND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
1995 Sep 22
8
Page 9
Philips Semiconductors Product specification
74ABT10Triple 3-input NAND gate
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1995
All rights reserved. Printed in U.S.A.
(print code) Date of release: July 1994 Document order number: 9397-750-04851
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