Datasheet 71413 Datasheet

Download

Page 1

P-Channel 20-V (D-S) MOSFET

Si5461EDC

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

0.045 at V

- 20

0.060 at V

0.082 at V

1206-8 ChipFET

Ordering Information: Si5461EDC-T1-E3 (Lead (Pb)-free) Si5461EDC-T1-GE3 (Lead (Pb)-free and Halogen-free)

Bottom View

(Ω)I

DS(on)

= - 4.5 V

= - 2.5 V

= - 1.8 V

Marking Code

LA XX

Part # Code

Lot Traceability and Date Code

(A)

- 6.2

- 5.4

- 4.6

FEATURES

• Halogen-free According to IEC 61249-2-21 Available

• ESD Protected

5000 V

5.4 k

P-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 5 s Steady State Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

= 150 °C)

Pulsed Drain Current

Continuous Source Current

Maximum Power Dissipation

Operating Junction and Storage Temperature Range

Soldering Recommendations (Peak Temperature)

c, d

TA = 25 °C

= 85 °C

TA = 25 °C

= 85 °C

, T

stg

- 6.2 - 4.5

- 4.5 - 3.2

- 2.1 - 1.1

- 20

± 12

- 20

2.5 1.3

1.3 0.7

- 55 to 150

260

°C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient

Maximum Junction-to-Foot (Drain) Steady State

t ≤ 5 s

Steady State 80 95

thJA

thJF

Notes: a. Surface Mounted on 1" x 1" FR4 board. b. When using HBM. The MM rating is 300 V. c. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result

of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.

d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.

Document Number: 71413 S09-0129-Rev. D, 02-Feb-09

40 50

°C/W

15 20

www.vishay.com

Page 2

Si5461EDC

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Gate Threshold Voltage

Gate-Body Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Diode Forward Voltage

Dynamic

Total Gate Charge

Gate-Drain Charge

Tur n -O n De l ay T i m e

Rise Time

Turn-Off Delay Time

Fall Time

GS(th)

GSS

DSS

D(on)

DS(on)

d(on)

d(off)

Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the de vice. These are stress rating s only, and functiona l operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

= VGS, ID = - 250 µA

VDS = 0 V, VGS = ± 4.5 V

= - 16 V, V

≤ - 5 V, V

= - 4.5 V, ID = - 5.0 A

= - 2.5 V, ID = - 4.0 A

= - 1.8 V, ID = - 2 A

= 0 V, TJ = 85 °C

VDS = - 5 V, ID = - 5.0 A

IS = - 1.1 A, V

= - 10 V, V

= - 10 V, RL = 10 Ω

≅ - 1 A, V

= - 4.5 V, ID = - 5.0 A

= - 4.5 V, RG = 6 Ω

GEN

= 0 V

= - 4.5 V

= 0 V

- 0.45 V

± 1.5

- 1

- 5

- 20 A

0.037 0.045

0.050 0.060

0.066 0.082

12 S

- 0.7 - 1.2 V

12.5 20

2.0

4.0

2.5 3.5

4.5 8.0

27 40

15 25

µA

nCGate-Source Charge

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

- Drain Current (A)I

www.vishay.com 2

VGS= 4.5 thru 2.5 V

1.5 V

0.5 V

0246810

- Drain-to-Source Voltage (V)

Output Characteristics

TC=-55°C

- Drain Current (A)I

0.0 0.5 1.0 1.5 2.0 2.5

VGS- Gate-to-Source Voltage (V)

25 °C

Transfer Characteristics

Document Number: 71413

S09-0129-Rev. D, 02-Feb-09

125 °C

Page 3

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.15

Si5461EDC

Vishay Siliconix

3000

C - Capacitance (pF)

- On-ResistanceR

DS(o n)

2500

2000

1500

1000

oss

500

rss

0 4 8 121620

iss

- Drain-to-Source Voltage (V)

Capacitance

1.6

VGS=4.5V I

=5.0A

1.4

1.2

1.0

(Normalized)

0.8

0.12

0.09 VGS=1.8V

- On-Resistance (Ω)R

0.06

DS(on)

0.03

0.00

0 4 8 12 16 20

- Drain Current (A)

VGS=2.5V

VGS=4.5V

On-Resistance vs. Drain Current

VDS=10V I

=5.0A

- Gate-to-Source Voltage (V)

0 5 10 15 20 25 30

100

- Source Current (A)I

0.1

0.01

0.0 0.2 0.4 0.6 0.8 1.0 1.2

VSD- Source-to-Drain Voltage (V)

Source-Drain Diode Forward Voltage

Document Number: 71413 S09-0129-Rev. D, 02-Feb-09

Qg- Total Gate Charge (nC)

Gate Charge

TJ= 150 °C

TJ=25 °C

0.6

- 50 - 25 0 25 50 75 100 125 150

- Junction Temperature (°C)

On-Resistance vs. Junction Temperature

0.30

0.25

0.20

0.15

- On-Resistance (Ω)R

0.10

DS(o n)

0.05

0.00 012345678

VGS- Gate-to-Source Voltage (V)

ID=5.0A

On-Resistance vs. Gate-to-Source Voltage

www.vishay.com

Page 4

Si5461EDC

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.4

0.3

ID= 250 µA

0.2

0.1

Variance (V)V

GS(th)

0.0

-0.1

-0.2

- 50 - 25 0 25 50 75 100 125 150

TJ- Temperature (°C)

Threshold Voltage

1000

(A)

GSS

800

600

400

TA=25°C

Pow er (W)

(A)

10 000

GSS

1000

100

0.1

-3

-1

-2

1 100 6001010

Time (s)

Single Pulse Power

150 °C

25 °C

200

024681012

VGS- Gate-to-Source Voltage (V)

Gate-Source Voltage vs. Gate Current

Duty Cycle = 0.5

0.2

0.1

Thermal Impedance

Normalized Effective Transient

0.05

0.02

Single Pulse

0.01

-4

-3

-2

Normalized Thermal Transient Impedance, Junction-to-Ambient

0.01

0.001

0.0001

-1

1 10 60010

Square Wave Pulse Duration (s)

1 100100.10

VGS- Gate-to-Source Voltage (V)

Gate-Source Voltage vs. Gate Current

Notes:

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

JM-TA=PDMZthJA

4. Surface Mounted

thJA

100

(t)

=80 °C/W

www.vishay.com 4

Document Number: 71413

S09-0129-Rev. D, 02-Feb-09

Page 5

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Duty Cycle = 0.5

0.2

0.1

0.01

0.05

0.02

Single Pulse

-4

-3

-2

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Foot

Thermal Impedance

Normalized Effective Transient

Si5461EDC

Vishay Siliconix

-1

11010

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71413

Document Number: 71413

www.vishay.com

S09-0129-Rev. D, 02-Feb-09

Page 6

1206-8 ChipFETR

Package Information

Vishay Siliconix

6578

3421

S b

NOTES:

1. All dimensions are in millimeaters.

2. Mold gate burrs shall not exceed 0.13 mm per side.

3. Leadframe to molded body offset is horizontal and vertical shall not exceed

4. Dimensions exclusive of mold gate burrs.

5. No mold flash allowed on the top and bottom lead surface.

0.08 mm.

2X 0.10/0.13 R

5678

4321

Backside View

DETAIL X

Document Number: 71151 15-Jan-04

MILLIMETERS INCHES

Dim Min Nom Max Min Nom Max

1.00 − 1.10 0.039 − 0.043

0.25 0.30 0.35 0.010 0.012 0.014

0.1 0.15 0.20 0.004 0.006 0.008

D E

e L S

ECN: C-03528—Rev. F, 19-Jan-04 DWG: 5547

0 − 0.038 0 − 0.0015

2.95 3.05 3.10 0.116 0.120 0.122

1.825 1.90 1.975 0.072 0.075 0.078

1.55 1.65 1.70 0.061 0.065 0.067

0.65 BSC 0.0256 BSC

0.28 − 0.42 0.011 − 0.017

0.55 BSC 0.022 BSC

5_Nom 5_Nom

www.vishay.com

Page 7

AN811

Vishay Siliconix

Single-Channel 1206-8 ChipFETr Power MOSFET Recommended

Pad Pattern and Thermal Performance

INTRODUCTION

New Vishay Siliconix ChipFETs in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. The 1206-8 ChipFET has the same footprint as the body of the LITTLE FOOTR TSOP-6, and can be thought of as a leadless TSOP-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger SO-8.

This technical note discusses the single-channel ChipFET 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance.

PIN-OUT

Figure 1 shows the pin-out description and Pin 1 identification for the single-channel 1206-8 ChipFET device. The pin-out is similar to the TSOP-6 configuration, with two additional drain pins to enhance power dissipation and thermal performance. The legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary.

Single 1206-8 ChipFET

26 mil

FIGURE 2. Footprint With Copper Spreading

The pad pattern with copper spreading shown in Figure 2 improves the thermal area of the drain connections (pins 1,2,3,6.7,8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. or

3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. An example of this method is implemented on the Vishay Siliconix Evaluation Board described in the next section (Figure 3).

THE VISHAY SILICONIX EVALUATION BOARD FOR THE SINGLE 1206-8

80 mil

68 mil

28 mil

Bottom View

FIGURE 1.

For package dimensions see the 1206-8 ChipFET package outline drawing (http://www.vishay.com/doc?71151).

BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286). This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads.

Document Number: 71126 12-Dec-03

The ChipFET 1206-08 evaluation board measures 0.6 in by

0.5 in. Its copper pad pattern consists of an increased pad area around the six drain leads on the top-side—approximately

0.0482 sq. in. 31.1 sq. mm—and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions. The outer package outline is for the 8-pin DIP, which will allow test sockets to be used to assist in testing.

The thermal performance of the 1206-8 on this board has been measured with the results following on the next page. The testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square FR4 pcb with copper on both sides of the board.

www.vishay.com

Page 8

AN811

Vishay Siliconix

Front of Board

ChipFETr

FIGURE 3.

THERMAL PERFORMANCE

Junction-to-Foot Thermal Resistance (the Package Performance)

Thermal performance for the 1206-8 ChipFET measured as junction-to-foot thermal resistance is 15_C/W typical, 20_C/W maximum for the single device. The “foot” is the drain lead of the device as it connects with the body. This is identical to the SO-8 package R shortening the leads to the point where they become only a small part of the total footprint area.

Junction-to-Ambient Thermal Resistance (dependent on pcb size)

The typical R 80_C/W steady state, compared with 68_C/W for the SO-8. Maximum ratings are 95_C/W for the 1206-8 versus 80_C/W for the SO-8.

performance, a feat made possible by

for the single-channel 1206-8 ChipFET is

Back of Board

vishay.com

The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 45_C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 33_C/W reduction was obtained by maximizing the copper from the drain on the larger 1” square pcb.

160

120

Thermal Resistance (C/W)

Min. Footprint

Single EVB

1” Square PCB

Testing

To aid comparison further, Figure 4 illustrates ChipFET 1206-8 thermal performance on two different board sizes and three different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of R

for the single 1206-8

ChipFET are :

1) Minimum recommended pad pattern (see

156_C/W

Figure 2) on the evaluation board size of

0.5 in x 0.6 in.

2) The evaluation board with the pad pattern

111_C/W

described on Figure 3.

3) Industry standard 1” square pcb with

78_C/W

maximum copper both sides.

www.vishay.com

-5

-3

-4

FIGURE 4. Single 1206−8 ChipFET

-1

-2

Time (Secs)

100 1000

1010

SUMMARY

The thermal results for the single-channel 1206-8 ChipFET package display similar power dissipation performance to the SO-8 with a footprint reduction of 80%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size.

ASSOCIATED DOCUMENT

1206-8 ChipFET Dual Thermal performance, AN812

(http://www.vishay.com/doc?71127).

Document Number: 71126

12-Dec-03

Page 9

Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET

0.093

(2.357)

0.080 (2.032)

0.036 (0.914)

0.022 (0.559)

Return to Index

0.026

(0.650)

0.016

(0.406)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.010

(0.244)

APPLICATION NOTE

www.vishay.com Document Number: 72593 2 Revision: 21-Jan-08

Page 10

Legal Disclaimer Notice

Vishay

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

Document Number: 91000 www.vishay.com Revision: 11-Mar-11 1