Page 1
查询6809供应商
A6810xA
OUT
1
OUT
8
2
OUT
7
3
OUT
CLOCK
GROUND
LOGIC
SUPPLY
STROBE
OUT
OUT
6
CLK
4
5
6
V
7
ST
8
5
910
4
LATCHES
REGISTER
REGISTER
LATCHES
DD
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD................... 7.0 V
Driver Supply Voltage, V
Continuous Output Current Range,
I
......................... -40 mA to +15 mA
OUT
Input Voltage Range,
V
....................... -0.3 V to VDD + 0.3 V
IN
Package Power Dissipation,
P
........................................ See Graph
D
Operating Temperature Range, T
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20
Storage Temperature Range,
T
............................... -55°C to +125°C
S
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
................... 60 V
BB
18
17
16
V
15
BB
14
13
BLNK
12
11
A
°C to +85°C
OUT
SERIAL
DATA OUT
LOAD
SUPPLY
SERIAL
DATA IN
BLANKING
OUT
OUT
OUT
Dwg. PP-029
26182.124B
6809
AND
Data Sheet
6810
DABiC-IV, 10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
The A6809– and A6810– devices combine 10-bit CMOS shift
registers, accompanying data latches and control circuitry with bipolar
sourcing outputs and pnp active pull downs. Designed primarily to
drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings
also allow these devices to be used in many other peripheral power
9
10
1
2
3
driver applications. The A6809– and A6810– feature an increased data
input rate (compared with the older UCN/UCQ5810-F) and a controlled output slew rate. The A6809xLW and A6810xLW are identical
except for pinout.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
typical serial-data input rates are up to 33 MHz.
A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are avail-able as
the A6811– (12 bits), A6812– (20 bits), and A6818– (32 bits).
The A6809– and A6810– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate
reduces electromagnetic noise, which is an important consideration in
systems that include telecommunications and/or microprocessors and
to meet government emissions regulations. For inter-digit blanking, all
output drivers can be disabled and all sink drivers turned on with a
BLANKING input high. The pnp active pull-downs will sink at least
2.5 mA.
All devices are available in two temperature ranges for optimum
performance in commercial (suffix S-) or industrial (suffix E-) applications. The A6810– is provided in three package styles for through-hole
DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area
surface-mount PLCC (suffix -EP). The A6809– is provided in the
SOIC (suffix -LW) only. Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow all devices to source
25 mA from all outputs continuously over the maximum operating
temperature range.
FEATURES
■ Controlled Output Slew Rate
■ High-Speed Data Storage
■ 60 V Minimum
Output Breakdown
■ High Data Input Rate
■ PNP Active Pull-Downs
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6810SLW .
■ Low Output-Saturation Voltages
■ Low-Power CMOS Logic
and Latches
■ Improved Replacements
for TL4810–, UCN5810–,
and UCQ5810–
Page 2
6809
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TYPICAL OUTPUT DRIVER TYPICAL INPUT CIRCUIT
V
BB
OUT
N
Dwg. EP-021-19
A6809xLW
NC
V
BLNK
BB
20
OUT
19
OUT
NO
18
CONNECTION
SERIAL
17
DATA OUT
16
LOAD SUPPLY
SERIAL
15
DATA IN
14
BLANKING
13
OUT
12
OUT
9
10
1
2
OUT
OUT
OUT
CLOCK
GROUND
CONNECTION
LOGIC SUPPLY
NO
STROBE
OUT
1
8
2
7
3
6
4
5
6
7
8
9
5
CLK
NC
V
ST
LATCHES
REGISTER
REGISTER
LATCHES
DD
CLOCK
NC
GROUND
LOGIC
SUPPLY
STROBE
V
DD
IN
Dwg. EP-010-5
A6810xEP
6
OUT
3
2
1
4
CLK
5
6
7
V
DD
8
ST
LATCHES
REGISTER
REGISTER
LATCHES
10
OUT
19
20
SERIAL
18
DATA OUT
V
BLNK
LOAD
17
BB
SUPPLY
NC
16
SERIAL
15
DATA IN
14
BLANKING
OUT
OUT
OUT
OUT
CLOCK
GROUND
LOGIC SUPPLY
STROBE
OUT
OUT
CONNECTION
NO
10 11
4
A6810xLW
1
8
2
7
3
6
4
CLK
5
6
7
ST
8
5
9
4
10
V
NC
LATCHES
REGISTER
REGISTER
LATCHES
DD
BLNK
OUT
3
Dwg. PP-029-9
9
5
OUT
12
11
10
13
1
OUT
Dwg. PP-059
2.5
20
OUT
9
19
OUT
10
SERIAL
18
DATA OUT
17
V
BB
NC
LOAD SUPPLY
SERIAL
16
DATA IN
15
BLANKING
14
OUT
13
OUT
12
OUT
NO
11
CONNECTION
Dwg. PP-029-2
1
2
3
SUFFIX 'EP', R = 59°C/W
2.0
1.5
1.0
0.5
0
25
θJA
SUFFIX 'A', R = 60°C/W
θJA
SUFFIX 'LW', R = 70°C/W
θJA
50 75 100 125 150
AMBIENT TEMPERATURE IN °C
Dwg. GP-024-1
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1998, 2000 Allegro MicroSystems, Inc.
Page 3
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FUNCTIONAL BLOCK DIAGRAM
6809
AND
6810
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
GROUND
OUT1OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
OUT
2
3
OUT
N
V
DD
MOS
BIPOLAR
V
BB
LOGIC
SUPPLY
SERIAL
DATA OUT
LOAD
SUPPLY
Dwg. FP-013-1
TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe
Input Input I
HHR
LLR
XR
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
1I2I3
1R2R3
XXX...X X X L R1R2R3... R
P1P2P3... P
1R2
1R2
... I
... R
... R
... R
N-1IN
N-2RN-1
N-2RN-1
N-1RN
N-1PN
Output Input I1I2I3... I
R
N-1
R
N-1
R
N
P
N
HP1P2P3... P
X X X ... X X H L L L ... L L
N-1IN
N-1 RN
N-1 PN
Blanklng I1I2I3... I
LP1P2P3... P
N-1
N-1 PN
I
N
Page 4
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6809SLW & A6810S-) or over operating
temperature range (A6809ELW & A6810E-), VBB = 60 V unless otherwise noted.
Limits @ VDD = 3.3 V Limits @ VDD = 5 V
Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units
V
Output Leakage Current I
Output Voltage V
Output Pull-Down Current I
Input Voltage V
Input Current I
Input Clamp Voltage V
Serial Data Output Voltage V
Maximum Clock Frequency f
Logic Supply Current I
Load Supply Current I
-to-
Blanking
Strobe
Output Fall Time t
Output Rise Time t
Output Delay t
-to-
Output Delay t
OUT(1)IOUT
V
OUT(0)IOUT
OUT(0)
V
I
OUT(1)IOUT
V
OUT(0)IOUT
DD(1)
I
DD(0)
BB(1)
I
BB(0)
dis(BQ)
t
en(BQ)
p(STH-QL)RL
t
p(STH-QH)RL
CEX
IN(1)
IN(0)
IN(1)
IN(0)
IK
c
f
r
= 0 V — <-0.1 -15 — <-0.1 -15 µA
OUT
= -25 mA 57.5 58.3 — 57.5 58.3 — V
= 1 mA — 1.0 1.5 — 1.0 1.5 V
V
= 5 V to V
OUT
VIN = V
DD
VIN = 0 V — <-0.01 -1.0 — <-0.01 -1.0 µA
IIN = -200 µA — -0.8 -1.5 — -0.8 -1.5 V
= -200 µA 2.8 3.05 — 4.5 4.75 — V
= 200 µA — 0.15 0.3 — 0.15 0.3 V
All Outputs High — 0.25 0.75 — 0.3 1.0 mA
All Outputs Low — 0.25 0.75 — 0.3 1.0 mA
All Outputs High, No Load — 1.5 3.0 — 1.5 3.0 mA
All Outputs Low — 0.2 20 — 0.2 20 µA
CL = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 µs
CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 µs
= 2.3 kΩ, CL ≤ 30 pF — 0.7 2.0 — 0.7 2.0 µs
= 2.3 kΩ, CL ≤ 30 pF — 1.8 3.0 — 1.8 3.0 µs
RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs
RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs
BB
2.5 5.0 — 2.5 5.0 — mA
2.2 ——3.3 —— V
——1.1 ——1.7 V
— <0.01 1.0 — <0.01 1.0 µA
10 33 — 10 33 — MHz
Output Slew Rate dV/dt RL = 2.3 kΩ, CL ≤ 30 pF 4.0 — 20 4.0 — 20 V/µs
Clock
-to-
Serial Data Out Delay t
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
p(CH-SQX)IOUT
= ±200 µA — 50 ——50 — ns
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Page 5
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
6809
AND
6810
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
STROBE
BLANKING
OUT
BLANKING
OUT
50%
A B
DATA
N
N
50%
t
p(CH-SQX)
t
p(STH-QH)
t
p(STH-QL)
10%
DATA
90%
t
dis(BQ)
50%
D E
50%
LOW = ALL OUTPUTS ENABLED
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
t
en(BQ)
t
r
DATA
10%
Dwg. WP-029
90%
DATA
t
f
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), t
......................................... 25 ns
su(D)
B. Data Active Time After Clock Pulse
(Data Hold Time), t
C. Clock Pulse Width, t
D. Time Between Clock Activation and Strobe, t
E. Strobe Pulse Width, t
............................................... 25 ns
h(D)
............................................... 50 ns
w(CH)
....... 100 ns
su(C)
............................................. 50 ns
w(STH)
NOTE – Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
www.allegromicro.com
Dwg. WP-030
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
Page 6
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
A6810EA & A6810SA
Dimensions in Inches
(controlling dimensions)
18
0.280
0.240
10
0.014
0.008
0.300
BSC
0.430
MAX
0.210
MAX
7.11
6.10
0.015
MIN
18
1
0.070
0.045
0.022
0.014
0.920
0.880
0.100
BSC
9
0.005
MIN
0.150
0.115
Dwg. MA-001-18A in
Dimensions in Millimeters
(for reference only)
0.355
10
1
1.77
1.15
23.37
22.35
2.54
BSC
9
0.13
MIN
0.204
7.62
BSC
10.92
MAX
5.33
MAX
0.39
MIN
0.558
0.356
3.81
2.93
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Dwg. MA-001-18A mm
Page 7
0.169
0.141
0.169
0.141
0.021
0.013
0.050
BSC
LATCHED SOURCE DRIVERS
A6810EEP & A6810SEP
Dimensions in Inches
(controlling dimensions)
14
0.395
0.385
0.032
0.026
0.356
0.350
18
6809
AND
6810
10-BIT SERIAL-INPUT,
913
8
INDEX AREA
4
0.020
MIN
0.180
0.165
Dimensions in Millimeters
0.533
0.331
4.29
3.58
1.27
BSC
4.29
3.58
4.57
4.20
NOTES: 1. Exact body and lead configuration at vendor’s
option within limits shown.
2. Lead spacing tolerance is non-cumulative.
0.51
MIN
10.03
9.78
19
(for reference only)
14
0.812
0.661
9.042
8.890
18
19
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
0.356
0.350
9.042
8.890
120 2
0.395
0.385
120 2
10.03
9.78
3
Dwg. MA-005-20A in
913
8
INDEX AREA
4
3
Dwg. MA-005-20A mm
www.allegromicro.com
Page 8
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
A6809ELW, A6809SLW, A6810ELW, & A6810SLW
Dimensions in Inches
(for reference only)
20 11
0.0125
0.0091
0.2992
0.2914
0.020
0.013
0.0926
0.1043
7.60
7.40
1 2
0.0040
20
MIN.
3
0.5118
0.4961
Dimensions in Millimeters
(controlling dimensions)
11
0.050
BSC
0.419
0.394
10.65
10.00
0° TO 8°
0.050
0.016
Dwg. MA-008-20 in
0.32
0.23
0.51
0.33
2.65
2.35
1
0.10
2
MIN.
3
13.00
12.60
1.27
BSC
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
0° TO 8°
Dwg. MA-008-20 mm
1.27
0.40
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