Datasheet 628128-70 Datasheet (FREI)

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 1 of 14

®

FEATURES

Access tim e :55ns

Low powe r consumption: Operating current:10 mA (TYP.) Standby c Single 2.7V ~ 5.5V po we r supply Fully Compatible with all Competitors 5V product

Fully Compatible with all Competitors 3.3V product

Fully static operation

Tri-state output

Data retention voltage : 1.5V (MIN.)

All products are ROHS Compliant

Package : 32-pin 450 mil SOP

urrent: 1 µA (TYP.)

32-pin 600 mil P-DIP 32-pin 8mm 32-pin 8mm

ball 6mm x 8mm TFBGA

36-

x 20mm TSOP-I x 13.4mm sTSOP

GENERA L DESCRIPTION

The AS6C1008 is a 1,048,57 6-bit low powe r CMOS static rand om access memory organized as 131,072 words by 8 bits. It is high performance, high reliability standby current is stable within the ra nge of operating te

mperature.

The AS6C1008 is well designed for ver system applications, and part icula rly well suited for battery

back-up non-volatile memory application.

The AS6C1008 operates from a single power supply of 2.7V ~ 5.5V.

.

fabricated using ve ry

CMO S technology. Its

y low power

FUNCTIONAL BLOCK DIAGRAM

Vcc Vss

A0-A16

DQ0-DQ7

CE#

CE2 WE# OE#

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

128Kx8

MEMORY ARRAY

COLUMN I/O

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A16 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE#, CE2 Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input V

C C

V

SS

NC No C onnection

Power Supply Ground

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 2 of 14

PIN CONFIGURATION

®

NC

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

DQ1

DQ2

Vss

Vcc

A15

CE2

WE#

A13

A8

A9

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

A11

A9 A8

A13

WE #

CE 2 A15 Vc c

NC A16 A14 A12

A7 A6 A5 A4 A3

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

AS6C1008

TS OP -I/sTSOP

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1716

OE #

A10 CE # DQ 7 DQ 6 DQ 5 DQ 4 DQ 3

Vss DQ 2 DQ 1 DQ 0

A0 A1 A2

A6A1 A3

A7

A15

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

1716

A8

DQ0

DQ1

Vcc

Vss

DQ2

DQ3

31A11A 21A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A0

A

DQ4

B

DQ5

C

Vss

D

Vcc

E

DQ6

F

DQ7

G

A9

H

AS6C1008

SOP/P-DIP

CE2

WE#

A4A2

CN 5A

NC

OE#

CE#

A16

A10 A14

1 2 3 4 5 6

TFBGA

.

®

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 3 of 14

ABSOLUTE MAXIMUM RATINGS*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS VTERM -0.5 to 7.0 V

0 to 70(C grade)

T erutarepmeT gnitarepO A

ºC

-40 to 85(I grade)

T erutarepmeT egarotS STG -65 to 150

ºC

P noitapissiD rewoP D 1 W

I tnerruC tuptuO CD OUT 50 mA

Soldering Temperature (under 10 sec) TSOLDER 260 ºC

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

Standby

Output Disable

Read

Write

Note: H = VIH, L = VIL, X = Don't care.

CE# CE2 OE# WE#

H X X X

X L X X

L H H H

L H L H

L H X L

DC ELECTRICAL CHARACTERISTICS

PARAMETER

Supply Voltage V Input High Voltage V Input Low Voltage V Input Leakage Current I Output Leakage Current Output High Voltage VOH I Output Low Voltage VOL I

Average Operating Power supply Current

Standby Power

Supply Current

*C=Commercial temperature/I= Industrial temperature

SYMBOL TEST CONDITION MIN. TYP.

CC

*1

IH

*2

IL

VCC≧ V

LI

V

I

LO

CC

Output Disabled

OH

OL

= 2mA - - 0.4 V

≧ V

IN

OUT

≧ V

Cycle time = Min.

I

CC

CE# = V

= 0mA

I

I/O

and CE2 = VIH,

IL

Cycle time = 1µs

≦

CE#

I

CC1

0.2V and CE2≧VCC-0.2V,

= 0mA

I

I/O

other pins at 0.2V or V

I

CE# V≧

SB1

or CE2≦0.2V

-0.2V

CC

SS

I/O OPERATION

High-Z I

High-Z ICC,I

D

ICC,I

OUT

DIN ICC,I

- 1 - 1

SS,

- 55 -

- 1 - 1

10 60

- 1 10 mA

-0.2V

CC

C*

- 1 20

I* - 1 50

SUPPLY CURRENT

SB1

CC1

*4

MAX. UNIT

V -ccV*7.0

+0.3 V

CC

µ

mA

µ

V 5.5 0.3 7.2

V 6.0 - 2.0 -

A

V - 7.2 2.2 Am1- =

A

®

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 4 of 14

Notes:

1. V

(max) = VCC+ 3.0V for pulse width less than 10ns.

IH

2. V

(min) = VSS- 3.0V for pulse width less than 10ns.

IL

3. Over/Undershoot specifications are characterized, not 100% tested.

4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at V

= VCC(TYP.) and TA= 25

CC

ºC

CAPACITANCE (TA = 25 , f℃ = 1.0MHz)

PARAMETER SYMBOL MIN. MAX UNIT

CecnaticapaCtupnI

IN

Input/Output Capacitance C

Note : These parameters are guaranteed by device characterization, but not production tested.

I/O

-

AC TEST CONDITIONS

VotV2.0sleveLesluPtupnI

- 0.2V

CC

sn3semiTllaFdnaesiRtupnI

Input and Output Timing Reference Levels 1.5V

CdaoLtuptuO

=30pF + 1TTL, I

L

OH/IOL

6 pF 8 pF

= -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER SYM.

AS6C1008-55 MIN. MAX.

Read Cycle Time t Address Access Time t Chip Enable Access Time t Output Enable Access Time t Chip Enable to Output in Low-Z t Output Enable to Output in Low-Z t Chip Disable to Output in High-Z t Output Disable to Output in High-Z t Output Hold from Address Change t

RC

AA

ACE

OE

* 10 - ns

CLZ

* 5 - ns

OLZ

* - 20 ns

CHZ

* - 20 ns

OHZ

OH

55 - ns

- 55 ns

- 30 ns

10 - ns

(2) WRITE CYCLE

PARAMETER SYM.

AS6C1008-55

MIN. MAX.

Write Cycle Time t Address Valid to End of Write t Chip Enable to End of Write t Address Set-up Time t Write Pulse Width t Write Recovery Time t Data to Write Time Overlap t Data Hold from End of Write Time t

WC

AW

CW

AS

WP

WR

DW

DH

55 - ns 50 - ns 50 - ns

0 - ns

45 - ns

0 - ns

25 - ns

0 - ns Output Active from End of Write tOW* 5 - ns Write to Output in High-Z t

*These parameters are guaranteed by device characterization, but not production tested.

* - 20 ns

WHZ

UNIT

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 5 of 14

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

tRC

Address

®

tOHtAA

Dout Data Valid

Previous Data Valid

READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)

tRC

Address

tAA

CE#

ACE

t

CE2

OE#

tOE

tOLZ

tCLZ

Dout Data Valid

tOH

tOHZ

tCHZ

High-ZHigh-Z

Notes :

1.WE# is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low

3.Address must be valid prior to or coincident with CE# = low,CE2 = high; otherwise tAA is the limiting parameter.

, t

4.t

CLZ

OLZ

5.At any given temperature and voltage condition, t

CHZ

and t

are specified with CL= 5pF. Transition is measured ±500mV from steady state.

OHZ

.,

is less than t

CHZ

CE2 = high

.

CLZ

, t

is less than t

OHZ

OLZ.

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 6 of 14

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

Address

tAW

CE#

CE2

®

tWC

tCW

tWP

WE#

tWHZ

Dout

(4)

Din

WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)

tWC

Address

tAW

CE# tWRtAS

tCW

CE2

tWP

High-Z

tDW tDH

Data Valid

tWRtAS

TOW

(4)

WE#

tWHZ

Dout

(4)

Din

Notes :

1.WE#, CE# must be high or CE2 must be low during all address transitions.

2.A write occurs during the overlap of a low CE#, high CE2, low WE#.

3.During a WE#controlled write cycle with OE# low, t

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high

impedance state.

6.t

and t

OW

are specified with CL= 5pF. Transition is measured ±500mV from steady state.

WHZ

must be greater than t

WP

High-Z

tDW tDH

Data Valid

+ tDW to allow the drivers to turn off and data to be

WHZ

®®

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 7 of 14

DATA RETENTION CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

VCCfor Data Retention V

CE# V≧

DR

or CE2 ≦ 0.2V

VCC= 1.5V

Data Retention Current I

DR

CE# V≧

or CE2 ≦ 0.2V

Chip Disable to Data Retention Time

t

CDR

Recovery Time t t

= Read Cycle Time C=Commercial temp/I = Industrial temp**

RC

*

See Data Retention Waveforms (below)

R

CC

- 0.2V

1.5 - 5.5 V

C** - 0.5 12 µA

I** 0 30

0 - - ns

t

RC

*

- - ns

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1)

Vcc

Vcc(min.)

CE#

(

controlled)

VDR ≧ 1.5V

Vcc(min.)

A

µ

V

CE#

IH

Low Vcc Data Retention Waveform (2)

Vcc

CE2

Vcc(min.)

V

IL

CE# V≧ cc-0.2V

(CE2 controlled)

VDR ≧ 1.5V

CE2 ≦ 0.2V

tRtCDR

VIH

Vcc(min.)

tRtCDR

VIL

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 8 of 14

PACKAGE OUTLINE DIMENSION

32 pin 450 mil SOP Package Outline Dimension

®

SYM.

A A1 A2

b

c D E

E1

e

L

L1

S

y

Θ

UNIT

INCH.(BASE) MM(REF)

0.118 (MAX) 2.997 (MAX)

0.004(MIN) 0.102(MIN)

0.111(MAX) 2.82(MAX)

0.016(TYP) 0.406(TYP)

0.008(TYP) 0.203(TYP)

0.817(MAX) 20.75(MAX)

0.445±0.005 11.303 ±0.127

0.555±0.012 14.097 ±0.305

0.050(TYP) 1.270(TYP)

0.0347±0.008 0.881 ±0.203

0.055±0.008 1.397 ±0.203

0.026(MAX) 0.660 (MAX)

0.004(MAX) 0.101(MAX)

o

0

-10o 0o -10

o

®®

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 9 of 14

32 pin 600 mil P-DIP Package Outline Dimension

A1 A2

B D E

E1

e

eB

L S

Q1

UNIT

INCH(BASE) MM(REF)

0.001 (MIN) 0.254 (MIN)

0.150 ± 0.005 3.810 ± 0.127

0.018 ± 0.005 0.457 ± 0.127

1.650 ± 0.005 41.910 ± 0.127

0.600 ± 0.010 15.240 ± 0.254

0.544 ± 0.004 13.818 ± 0.102

0.100 (TYP) 2.540 (TYP)

0.640 ± 0.020 16.256 ± 0.508.

0.130 ± 0.010 3.302 ± 0.254

0.075 ± 0.010 1.905 ± 0.254

0.070 ± 0.005 1.778 ± 0.127

SYM.

Note : D/E1/S dimension do not include mold flash.

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 10 of 14

32 pin 8mm x 20mm TSOP-I Package Outline Dimension

®

SYM.

A

A1 A2

b

c D E

e

HD

L

L1

y

Θ

UNIT

INCH(BASE) MM(REF)

0.047 (MAX) 1.20 (MAX)

0.004±0.002 0.10±0.05

0.039±0.002 1.00±0.05

0.008 + 0.002

0.20 + 0.05

- 0.001

0.005 (TYP) 0.127 (TYP)

0.724±0.004 18.40±0.10

0.315±0.004 8.00±0.10

0.020 (TYP) 0.50 (TYP)

0.787±0.008 20.00±0.20

0.0197±0.004 0.50±0.10

0.0315±0.004 0.08±0.10

0.003 (MAX) 0.076 (MAX)

o

～

5

0

o

0

～

5

-0.03

o

®®

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 11 of 14

32 pin 8mm x 13.4mm sTSOP Package Outline Dimension

HD

c

L

1

16

32

17

"A"

D

12° (2x)12° (2x)

e

b

Seating Plane

E

y

12° (2X)

16

1

A

A1 A2

b

c D E

e

HD

L

L1

y

Θ

UNIT

0.049 (MAX) 1.25 (MAX)

0.005±0.002 0.130±0.05

0.039±0.002 1.00±0.05

0.008±0.01 0.20±0.025

0.005 (TYP) 0.127 (TYP)

0.465±0.004 11.80±0.10

0.315±0.004 8.00±0.10

0.020 (TYP) 0.50 (TYP)

0.528±0.008 13.40±0.20.

0.0197±0.004 0.50±0.10

0.0315±0.004 0.8±0.10

0.003 (MAX) 0.076 (MAX) 0

SYM.

17

c

A2A1

A

SEATING PLANE

"A" DETAIL VIEW

32

INCH(BASE) MM(REF)

o

～

o

5

o

～

0

5

12° (2X)

GAUGE PLANE

0.254

0

L

L1

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 12 of 14

36 ball 6mm × 8mm TFBGA Package Outline Dimension

®

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 14 of 14

Alliance Memory, Inc. 1116 South Amphlett, #2, San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449

Part Number: AS6C1008

Document Version: v. 1.0

www.alliancememory.com

Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.