Page 1
6277
Selection Guide
Part Number Pb-free* Package Packing
Ambient
Temperature (°C)
A6277EA-T Yes 20-pin DIP 18 per tube –40 to 85
A6277ELW-T Yes 20-pin SOICW 37 per tube –40 to 85
A6277ELWTR-T Yes 20-pin SOICW 1000 per reel –40 to 85
*Pb-based variants are being phased out of the product line. The variants cited in this
footnote are in production but have been determined to be NOT FOR NEW DESIGN.
This classification indicates that sale of this device is currently restricted to existing
customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer
available. Status change: May 1, 2006. These variants include: A6277EA, A6277ELW,
A6277ELWTR, A6277SA, A6277SLW, and A6277SLWTR.
8-BIT SERIAL-INPUT, CONSTANTCURRENT LATCHED LED DRIVER
2
D
6
a
1
t
a
8
5
S
.
2
h
0
e
2
e
c
t
The A6277x is specifically designed for LED-display applications.
Each BiCMOS device includes an 8-bit CMOS shift register, accompanying data latches, and eight npn constant-current sink drivers. Two
package styles and two operating temperature ranges are available.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V logic supply, typical serial
data-input rates are up to 20 MHz. The LED drive current is determined by the user’s selection of a single resistor. A CMOS serial data
output permits cascade connections in applications requiring additional
drive lines. For inter-digit blanking, all output drivers can be disabled
with an ENABLE input high. In addition, a HIGH/LOW function
enables full selected current with the application of a logic low, or 50%
selected current with the application of a logic high.
The first character of the part number suffix determines the device
operating temperature range. Suffix ‘E–’ is for -40°C to +85°C, and
LOGIC
GROUND
SERIAL
DATA IN
CLOCK
LATCH
ENABLE
HIGH/LOW
(CURRENT)
POWER
GROUND
OUT
OUT
OUT
OUT
A6277ELW
1
2
CK
3
L
4
5
6
SUB
7
0
8
1
9
2
10
3
REGULATOR
REGISTER
LATCHES
V
I
O
FF
OE
SUB
LOGIC
20
DD
SUPPLY
R
19
EXT
SERIAL
18
17
16
15
14
13
12
11
DATA OUT
SERIAL
DATA OUT
OUTPUT
ENABLE
POWER
GROUND
OUT
OUT
OUT
OUT
1
2
7
6
5
4
suffix ‘S–’ is -20°C to +85°C. Two package styles are provided for
Dwg. PP-029-17A
Note that the A6277EA (DIP) and the A6277ELW
(SOIC) are electrically identical and share a
common terminal number assignment.
through-hole DIP (suffix ‘–A’) or surface-mount SOIC (suffix ‘–LW’)
applications. The copper lead frame and low logic-power dissipation
allow the dual in-line package to sink 122 mA through all outputs
continuously over the operating temperature range (1.0 V drop,
+85°C).
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD...................... 7.0 V
Output Voltage Range,
VO............................ -0.5 V to +24 V
Output Current, I
Input Voltage Range,
VI.................... -0.4 V to VDD + 0.4 V
Package Power Dissipation,
....................... 150 mA
O
FEATURES
■ To 150 mA Constant-Current Outputs
■ Under-Voltage Lockout
■ Low-Power CMOS Logic and Latches
■ High Data Input Rate
■ Similar to Toshiba TD62715FN
■ High/Low Output Current Function
PD..................................... See Graph
Operating Temperature Range, T
A
Suffix ‘S-’ ................ -20°C to +85°C
Suffix ‘E-’ ................ -40°C to +85°C
Storage Temperature Range,
TS........................... -55°C to +150°C
Caution: These CMOS devices have input
static protection (Class 2) but are still susceptible to damage if exposed to extremely high
static electrical charges.
Digital “Dim” Control
Page 2
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
2.5
2.0
1.5
1.0
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
25
SUFFIX 'A', R = 55°C/W
50 75 100 125 150
AMBIENT TEMPERATURE IN °°°°C
θJA
SUFFIX 'LW', R = 70°C/W
θJA
Dwg. GP-018-1
FUNCTIONAL BLOCK DIAGRAM
UVLO
V
DD
LOGIC
SUPPLY
CLOCK
SERIAL
DATA IN
LATCH
ENABLE
LOGIC
GROUND
POWER
GROUND
POWER
GROUND
Dwg. FP-013-7
2
SUB
OUT0OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
OUT
1
2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2001, 2003 Allegro MicroSystems, Inc.
OUT
N
FF
MOS
BIPOLAR
I
O
REGULATOR
SERIAL DATA
OUT
2
SERIAL DATA
OUT
1
OUTPUT ENABLE
(ACTIVE LOW)
HIGH/LOW
(CURRENT)
R
EXT
Page 3
6277
DD
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
V
DD
V
DD
IN
Dwg. EP-010-11
IN
Dwg. EP-010-12
LATCH ENABLE and HIGH/LOWOUTPUT ENABLE (active low)
V
DD
IN
Dwg. EP-063-6
Dwg. EP-010-13
V
CLOCK and SERIAL DATA IN SERIAL DATA OUT
OUT
TRUTH TABLE
Serial Shift Register Contents Serial Latch Latch Contents Output Output Contents
Data Clock Data Enable Enable
Input Input I
1I2I3
HHR
LLR
XR
1R2R3
XXX...X X X L R1R2R3... R
P1P2P3... P
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
1R2
1R2
... I
N-1IN
... R
N-2RN-1RN-1
... R
N-2RN-1RN-1
... R
N-1RN
N-1PN
Output Input I1I2I3... I
R
N
P
N
HP1P2P3... P
XXX...X X H H H H ... H H
N-1IN
N-1 RN
N-1 PN
Input I1I2I3... I
LP1P2P3... P
I
N-1
N-1 PN
N
3
Page 4
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ELECTRICAL CHARACTERISTICS at T
= +25°C, V
A
= VDD = 5 V (unless otherwise noted).
H/L
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage Range V
Under-Voltage Lockout V
Output Current I
DD
DD(UV)
O
(any single output)
Output Current Matching ∆I
O
(difference between any R
two outputs at same VCE)
Output Leakage Current I
Logic Input Voltage V
SERIAL DATA OUT Voltage V
(SDO1 & SDO2)
CEX
V
V
IH
IL
OL
OH
Operating 4.5 5.0 5.5 V
VDD = 0 to 5 V 3.4 – 4.0 V
VCE = 1.0 V, R
VCE = 0.4 V, R
0.4 V ≤ V
V
OH
CE(A)
EXT
R
EXT
= 20 V – 1.0 5.0 µA
= 160 Ω 100 120 140 mA
EXT
= 470 Ω 34 42 48 mA
EXT
= V
CE(B)
≤ 1.0 V:
= 160 Ω – ±1.5 ±6.0 %
= 470 Ω – ±1.5 ±6.0 %
0.7V
– – 0.3V
––V
DD
DD
IOL = 1.0 mA – – 0.4 V
IOH = -1.0 mA 4.6 – – V
V
Input Resistance R
I
ENABLE input, pull up 150 300 600 kΩ
LATCH & HIGH/LOW inputs, pull down 100 270 400 kΩ
Supply Current I
DD(OFF)
I
DD(ON)
R
= open, VOE = 5 V – 0.8 1.6 mA
EXT
R
= 470 Ω, V
EXT
R
= 160 Ω, V
EXT
R
= 470 Ω, V
EXT
R
= 160 Ω, V
EXT
Typical Data is at VDD = 5 V and is for design information only.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
= 5 V 3.5 6.5 9.5 mA
OE
= 5 V 14 17 22 mA
OE
= 0 V 5.0 10 15 mA
OE
= 0 V 20 27 40 mA
OE
Page 5
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
SWITCHING CHARACTERISTICS at T
R
EXT
= 470
ΩΩ
Ω, I
= 40 mA, VL = 3 V, RL = 65
ΩΩ
O
= 25°C, V
A
ΩΩ
Ω, C
ΩΩ
= VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
DD
= 10.5 pF.
L
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Propagation Delay Time t
Propagation Delay Time t
Output Fall Time t
Output Rise Time t
pHL
pLH
f
r
CLOCK-OUT
LATCH-OUT
ENABLE-OUT
n
n
n
CLOCK-SERIAL DATA OUT
CLOCK-OUT
LATCH-OUT
ENABLE-OUT
n
n
n
CLOCK-SERIAL DATA OUT
1
2
– 350 1000 ns
– 350 1000 ns
– 350 1000 ns
–40– ns
– 300 1000 ns
– 400 1000 ns
– 380 1000 ns
–40– ns
90% to 10% voltage 150 250 1000 ns
10% to 90% voltage 150 250 600 ns
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Conditions Min. Typ. Max. Unit
Supply Voltage V
Output Voltage V
Output Current I
Logic Input Voltage V
Clock Frequency f
www.allegromicro.com
DD
O
O
I
OH
I
OL
IH
V
IL
CK
Continuous, any one output – – 150 mA
SERIAL DATA OUT – – -1.0 mA
SERIAL DATA OUT – – 1.0 mA
Cascade operation – – 10 MHz
4.5 5.0 5.5 V
– 1.0 4.0 V
0.7V
– – 0.3V
–– V
DD
DD
V
5
Page 6
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT.
SERIAL
DATA OUT.
LATCH
ENABLE
OUTPUT
ENABLE
OUT
OUTPUT
ENABLE
OUT
1
N
2
N
50%
A B
DATA
50%
t
p
50%
t
p
D E
50%
LOW = ALL OUTPUTS ENABLED
HIGH = ALL OUTPUTS DISABLED (BLANKED)
50%
F
90%
t
pHL
DATA
DATA50%
t
p
t
pLH
HIGH = OUTPUT OFF
50%
LOW = OUTPUT ON
Dwg. WP-029-3
t
ftr
DATA
50%
10%
DATA
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), t
.......................................... 60 ns
su(D)
B. Data Active Time After Clock Pulse
(Data Hold Time), t
C. Clock Pulse Width, t
.............................................. 20 ns
h(D)
............................................... 50 ns
w(CK)
D. Time Between Clock Activation
and Latch Enable, t
E. Latch Enable Pulse Width, t
F. Output Enable Pulse Width, t
............................................ 100 ns
su(L)
................................... 100 ns
w(L)
................................ 4.5 µs
w(OE)
NOTE – Timing is representative of a 10 MHz clock.
Significantly higher speeds are attainable.
— Max. Clock Transition Time, tr or tf.............................. 10 µs
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Dwg. WP-030-1A
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-toparallel conversion). The latches will continue to accept new
data as long as the LATCH ENABLE is held high. Applications where the latches are bypassed (LATCH ENABLE tied
high) will require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
Page 7
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
A6277xA A6277xLW
6277
140
120
100
80
60
40
20
TA = +25°C
DD
= 5 V
V
θ
JA
= 55°C/W
R
ALLOWABLE OUTPUT CURRENT IN mA/BIT
0
020
DUTY CYCLE IN PER CENT
140
120
100
80
60
VCE = 4 V
VCE = 4 V
6040
VCE = 3 V
VCE = 3 V
VCE = 1 V
VCE = 2 V
Dwg. GP-062-17
VCE = 1 V
VCE = 2 V
140
120
100
VCE = 3 V
80
60
40
20
TA = +25°C
DD
= 5 V
V
θ
JA
= 70°C/W
R
VCE = 4 V
VCE = 1 V
VCE = 2 V
ALLOWABLE OUTPUT CURRENT IN mA/BIT
10080
0
020
140
120
100
80
60
6040
DUTY CYCLE IN PER CENT
VCE = 3 V
VCE = 4 V
10080
Dwg. GP-062-16
VCE = 1 V
VCE = 2 V
40
20
TA = +50°C
DD
= 5 V
V
θ
JA
= 55°C/W
R
ALLOWABLE OUTPUT CURRENT IN mA/BIT
0
020
DUTY CYCLE IN PER CENT
www.allegromicro.com
40
20
TA = +50°C
DD
= 5 V
V
θ
JA
= 70°C/W
R
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
10080
Dwg. GP-062-15
0
020
DUTY CYCLE IN PER CENT
6040
10080
Dwg. GP-062-14
7
Page 8
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6277xA A6277xLW
140
120
100
80
60
40
20
TA = +85°C
DD
= 5 V
V
θ
JA
= 55°C/W
R
VCE = 4 V
ALLOWABLE OUTPUT CURRENT IN mA/BIT
0
020
DUTY CYCLE IN PER CENT
VCE = 3 V
6040
VCE = 0.7 V
VCE = 1 V
VCE = 2 V
140
120
100
80
60
40
20
ALLOWABLE OUTPUT CURRENT IN mA/BIT
0
10080
Dwg. GP-062-13
020
TYPICAL CHARACTERISTICS
VCE = 4 V
TA = +85°C
DD
= 5 V
V
θ
JA
= 70°C/W
R
DUTY CYCLE IN PER CENT
VCE = 3 V
VCE = 2 V
6040
VCE = 0.7 V
VCE = 1 V
10080
Dwg. GP-062-12
60
40
20
TA = +25°C
R
EXT
= 470 Ω
OUTPUT CURRENT IN mA/BIT
0
0
0.5
1.0
1.5
VCE IN VOLTS
2.0
Dwg. GP-063-1
115 Northeast Cutoff, Box 15036
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
Page 9
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
TERMINAL DESCRIPTION
Terminal No. Terminal Name Function
1 LOGIC GROUND Reference terminal for control logic.
2 SERIAL DATA IN Serial-data input to the shift-register.
3 CLOCK Clock input terminal for data shift on rising edge.
4 LATCH ENABLE Data strobe input terminal; serial data is latched with high-level input.
5 HIGH/LOW Logic low for 100% of programmed current level;
(CURRENT) logic high for 50% of programmed current level.
6 POWER GROUND Ground.
6277
7-14 OUT
0-7
The eight current-sinking output terminals.
15 POWER GROUND Ground.
16 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
17 SERIAL OUT
18 SERIAL OUT
2
1
CMOS serial-data output (on clock falling edge).
CMOS serial-data output (on clock rising edge)
to the following shift-registers.
19 R
EXT
An external resistor at this terminal establishes the output current for all sink
drivers.
20 LOGIC SUPPLY (V
) The logic supply voltage. Typically 5 V.
DD
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
9
Page 10
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
Applications Information
The load current per bit (IO) is set by the external resistor
(R
) as shown in the figure below.
EXT
140
120
100
80
60
40
OUTPUT CURRENT IN mA/BIT
20
0
100
CURRENT-CONTROL RESISTANCE, R
300 500 700 1 k
200
Package Power Dissipation (P
). The maximum allow-
D
VCE = 0.7 V
2 k
EXT
IN OHMS
3 k
Dwg. GP-061-1
able package power dissipation is determined as
PD(max) = (150 - TA)/R
θJA
.
The actual package power dissipation is
PD(act) = dc(VCE • IO • 8) + (VDD • IDD).
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if P
reducer (V
(act) > PD(max), an external voltage
D
) should be used.
DROP
5 k
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
provide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
White 3.5 – 4.0 V
Blue 3.0 – 4.0 V
Green 1.8 – 2.2 V
Yellow 2.0 – 2.1 V
Amber 1.9 – 2.65 V
Red 1.6 – 2.25 V
Infrared 1.2 – 1.5 V
Pattern Layout. This device has separate logic-ground
and power-ground terminals. If ground pattern layout
contains large common-mode resistance, and the voltage
between the system ground and the LATCH ENABLE or
CLOCK terminals exceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
V
LED
V
DROP
Load Supply Voltage (V
). These devices are de-
LED
signed to operate with driver voltage drops (VCE) of 0.4 V
to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is recommended to use the lowest possible load supply voltage or
to set any series dropping voltage (V
V
with V
DROP
= Io • R
DROP
DROP
= V
- VF - V
LED
for a single driver, or a Zener
DROP
) as
CE
diode (VZ), or a series string of diodes (approximately
10
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
V
F
V
CE
Dwg. EP-064
Page 11
0.280
0.240
20
A6277EA
Dimensions in Inches
(controlling dimensions)
11
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
0.014
0.008
0.430
MAX
0.300
BSC
0.210
MAX
7.11
6.10
0.015
MIN
20
1
0.070
0.045
0.022
0.014
1.060
0.980
0.100
BSC
10
0.005
MIN
0.150
0.115
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
0.355
11
1
1.77
1.15
26.92
24.89
2.54
BSC
10
0.13
MIN
0.204
7.62
BSC
10.92
MAX
5.33
MAX
0.39
MIN
0.558
0.356
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 18 devices.
www.allegromicro.com
3.81
2.93
Dwg. MA-001-20 mm
11
Page 12
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
A6277ELW
Dimensions in Inches
(for reference only)
0.2992
0.2914
0.020
0.013
0.0926
0.1043
20 11
1 2
3
0.5118
0.4961
0.0040
MIN.
Dimensions in Millimeters
(controlling dimensions)
11
0.050
BSC
0.0125
0.0091
0.419
0.394
0.050
0.016
0° TO 8°
Dwg. MA-008-20 in
0.32
0.23
7.60
7.40
0.51
0.33
2.65
2.35
1202
0.10
MIN.
3
13.00
12.60
1.27
BSC
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 37 devices or add “TR” to part number for tape and reel.
12
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10.65
10.00
1.27
0.40
0° TO 8°
Dwg. MA-008-20 mm
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