Datasheet 62256-80 Datasheet (FREI)

HY62CT08081E Series

32Kx8bit CMOS SRAM

Document Title

32K x8 bit 5.0V Low Power Slow SRAM

Revision History

Revision No History Draft Date Remark

00 Initial Nov.01.2000 Preliminary 01 Marking Information Add Dec.05.2000 Preliminary

Revised

- DC / AC Characteristics

- AC Test Condition Add : 5pF Test Load

02 Revised Feb.13.2001 Final

- Remove L-Part

- Change LL-Part Isb1 Limit @E.T/I.T

: 15uA => 20uA

03 Revised Feb.21.2001 Final

- Marking Information Change : SOP Type

04 Changed Logo Apr.30.2001 Final

- HYUNDAI -> hynix

- Marking Information Change

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied.

Rev 04 / Apr. 2001 Hynix Semiconductor

HY62CT08081E Series

28 pin 600mil PDIP

/WE

OUTPUT BUFFER

DESCRIPTION

The HY62CT08081E is a high-speed, low power and 32,786 X 8-bits CMOS Static Random Access Memory fabricated using Hynix's high performance CMOS process technology. It is suitable for use in low voltage operation and battery back-up application. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0 volt.

Product Voltage Speed Operation Standby Current(uA) Temperature

No. (V) (ns) Current(mA) HY62CT08081E-C HY62CT08081E-E 5.0 55/70/85 HY62CT08081E-I 5.0 55/70/85 Note 1. Current value is max.

5.0 55/70/85

PIN CONNECTION

10 10 0~70(Normal) 10 20 -25~85(Extended) 10 20 -40~85(Industrial)

FEATURES

• Fully static operation and Tri-state output

• TTL compatible inputs and outputs

• Low power consumption

• Battery backup

- 2.0V(min.) data retention

• Standard pin configuration

-

- 28 pin 330mil SOP

- 28 pin 8x13.4 mm TSOP-I (Standard)

LL

(°C)

A14 A12

A7 A6 A5 A4 A3 A2 A1

A0 I/O1 I/O2 I/O3

Vss

1 2 3 4 5 6 7 8

9 10 11 12 13 14

Vcc

28 27 26 25 24 23 22 21 20 19 18 17 16 15

/WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4

A14 A12

A7 A6 A5 A4 A3 A2 A1

A0 I/O1 I/O2 I/O3

Vss

1 2 3 4 5 6 7 8

9 10 11 12 13 14

Vcc

28

/WE

27 26 25 24 23 22 21 20 19 18 17 16 15

A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4

/OE A11

A13 Vcc

A14 A12

1 2

A9

3

A8

4 5 6 7 8 9

10

A7

11

A6 A5

12 13

A4

14

A3

A10

28

/CS

27

I/O8

26

I/O7

25

I/O6

24

I/O5

23

I/O4

22

Vss

21

I/O3

20

I/O2

19

I/O1

18

A0

17

A1

16

A2

15

PDIP SOP TSOP-I(Standard)

PIN DESCRIPTION BLOCK DIAGRAM

Pin Name Pin Function

A0

ROW DECODER

I/O1

/CS Chip Select /WE Write Enable /OE Output Enable A0 ~ A14 Address Inputs I/O1 ~ I/O8 Data Input/Output Vcc

Power(+5.0V)

Vss Ground

/CS

/OE

/WE

A14

MEMORY ARRAY

ADD INPUT BUFFER

COLUMN DECODER

LOGIC

CONTROL

512x512

SENSE AMP

I/O8

WRITE DRIVER

Rev 04 / Apr. 2001

2

HY62CT08081E Series

ORDERING INFORMATION

Part No. Speed Power Temp Package

HY62CT08081E-DPC 55/70/85 LL-part HY62CT08081E-DPE 55/70/85 LL-part HY62CT08081E-DPI 55/70/85 LL-part HY62CT08081E-DGC 55/70/85 LL-part HY62CT08081E-DGE 55/70/85 LL-part HY62CT08081E-DGI 55/70/85 LL-part HY62CT08081E-DTC 55/70/85 LL-part HY62CT08081E-DTE 55/70/85 LL-part HY62CT08081E-DTI 55/70/85 LL-part

ABSOLUTE MAXIMUM RATING (1)

Symbol Parameter Rating Unit Vcc, VIN, VOUT Power Supply, Input/Output Voltage -0.3 to 7.0 V TA Operating Temperature

TSTG Storage Temperature -65 to 150 PD Power Dissipation 1.0 W IOUT Data Output Current 50 mA TSOLDER Lead Soldering Temperature & Time Note

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

Vcc Power Supply Voltage 4.5 5.0 5.5 V Vss Ground 0 0 0 V VIH Input High Voltage 2.2 - Vcc+0.3 VIL Input Low Voltage -0.3(1) - 0.8 V Note

1. VIL = -3.0V for pulse width less than 50ns

0 to 70°C

-25 to 85°C

-40 to 85°C 0 to 70°C

-25 to 85°C

-40 to 85°C 0 to 70°C

-25 to 85°C

-40 to 85°C

HY62CT08081E-C 0 to 70 HY62CT08081E-E -25 to 85 HY62CT08081E-I -40 to 85

PDIP

SOP

TSOP-I Standard

260 •10 °C•sec

V

°C °C °C °C

Rev 04 / Apr. 2001

2

HY62CT08081E Series

TRUTH TABLE

/CS /WE /OE

H X X Standby High-Z

L H H Output Disabled High-Z L H L Read Data Out L L X Write Data In

Note

1. H=VIH, L=VIL, X=Don't Care

DC CHARACTERISTICS

Vcc = 5V ±10%, TA = 0°C to 70°C (Normal) / -25°C to 85°C (Extended) / -40°C to 85°C (Industrial), unless otherwise specified.

Symbol

ILI Input Leakage Current Vss < VIN < Vcc -1 - 1 uA ILO Output Leakage Current Vss < VOUT < Vcc, /CS = VIH or

Icc Operating Power Supply

Current

ICC1 Average Operating Current /CS = VIL, VIN = VIH or VIL, ISB TTL Standby Current

(TTL Inputs) ISB1 CMOS Standby Current /CS > Vcc - 0.2V, (CMOS Inputs) VIN > Vcc - 0.2V or VIN < Vss + 0.2V

VOL Output Low Voltage IOL = 2.1mA - - 0.4 V VOH Output High Voltage IOH = -1.0mA 2.4 - - V

Note : Typical values are at Vcc =5.0V, TA = 25°C

Parameter Test Condition Min. Typ. Max. Unit

Mode I/O Operation

/OE = VIH or /WE = VIL

/CS = VIL, VIN = VIH or VIL, II/O = 0mA

Min. Duty Cycle = 100%, II/O = 0mA /CS= VIH, VIN = VIH or VIL

0~70°C

-25~85°C or

-40~85°C

-1 - 1 uA

- - 10 mA

- - 50 mA

- - 1 mA

- - 10 uA

- - 20 uA

Rev 04 / Apr. 2001

3

READ CYCLE

WRITE CYCLE

HY62CT08081E Series

AC CHARACTERISTICS

Vcc = 5V ±10%, TA = 0°C to 70°C (Normal) / -25°C to 85°C (Extended) / -40°C to 85°C (Industrial) unless otherwise specified.

Symbol

#

1 tRC Read Cycle Time 55 - 70 - 85 - ns 2 tAA Address Access Time - 55 - 70 - 85 ns 3 tACS Chip Select Access Time - 55 - 70 - 85 ns 4 tOE Output Enable to Output Valid - 25 - 35 - 45 ns 5 tCLZ Chip Select to Output in Low Z 10 - 10 - 10 - ns 6 tOLZ Output Enable to Output in Low Z 5 - 5 - 5 - ns 7 tCHZ Chip Disable to Output in High Z 0 20 0 30 0 30 ns 8 tOHZ Out Disable to Output in High Z 0 20 0 30 0 30 ns 9 tOH Output Hold from Address Change 5 - 5 - 5 - ns

10 tWC Write Cycle Time 55 - 70 - 85 - ns 11 tCW Chip Selection to End of Write 45 - 60 - 75 - ns 12 tAW Address Valid to End of Write 45 - 60 - 75 - ns 13 tAS Address Set-up Time 0 - 0 - 0 - ns 14 tWP Write Pulse Width 40 - 50 - 60 - ns 15 tWR Write Recovery Time 0 - 0 - 0 - ns 16 tWHZ Write to Output in High Z 0 20 0 25 0 30 ns 17 tDW Data to Write Time Overlap 25 - 30 - 40 - ns 18 tDH Data Hold from Write Time 0 - 0 - 0 - ns 19 tOW Output Active from End of Write 5 - 5 - 5 - ns

Parameter

AC TEST CONDITIONS

TA = 0°C to 70°C (Normal) / -25°C to 85°C (Extended) / -40°C to 85°C (Industrial) unless otherwise specified.

Parameter Value

Input Pulse Level 0.8V to 2.4V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load tCLZ,tOLZ,tCHZ,tOHZ,tWHZ,tOW CL = 5pF + 1TTL Load Others CL = 100pF + 1TTL Load

-55 -70 -85

Min. Max. Min. Max. Min Max.

Unit

Rev 04 / Apr. 2001

4

HY62CT08081E Series

AC TEST LOADS

TTL

CL(1)

Note : Including jig and scope capacitance

CAPACITANCE

TA = 25°C, f = 1.0MHz

Symbol Parameter Condition Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

CI/O Input /Output Capacitance VI/O = 0V 8 pF

Note : These parameters are sampled and not 100% tested

Rev 04 / Apr. 2001

5

HY62CT08081E Series

ADDR

OE

Out

Data Valid

tRC

tACS

tCLZ

tOE

tAA

tOHZ

tCHZ

tRC

tAA

TIMING DIAGRAM

READ CYCLE 1

tOH

CS

Data

tOLZ

High-Z

Note(READ CYCLE):

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and arenot referenced to output voltage levels.

2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device.

3. /WE is high for the read cycle.

READ CYCLE 2

ADDR

tOH

Data Out

tOH

Data ValidPrevious Data

Note(READ CYCLE):

1. /WE is high for the read cycle.

2. Device is continuously selected /CS= VIL.

3. /OE =VIL.

Rev 04 / Apr. 2001

6

HY62CT08081E Series

OE

tWC

tOHZ

WE

tWP

Data In

tWR

tCW

tAW

tWHZ

tDH

tWP

tAS

tWR

tCW

tAW

(8)

tOW

CS

tWC

WRITE CYCLE 1(/OE Clocked)

ADDR

CS

tAS

Data Out

WRITE CYCLE 2 (/OE Low Fixed)

ADDR

WE

Data In

tDW

tDH

Data Valid

Data Out

(7)

Rev 04 / Apr. 2001

7

HY62CT08081E Series

VSS

2.2V

Notes(WRITE CYCLE):

1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition

among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the later of /CS going low to the end of write .

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS, or /WE going high.

5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,

input of opposite phase of the output must not be applied because bus contention can occur.

6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high

impedance state.

7. DOUT is the same phase of the latest written data in this write cycle.

8. DOUT is the read data of the new address.

DATA RETENTION CHARACTERISTIC

TA = 0°C to 70°C (Normal) / -25°C to 85°C (Extended) / -40°C to 85°C (Industrial) unless otherwise specified.

Symbol

VDR Vcc for Data Retention CS>Vcc-0.2V, 2.0 - - V VIN>Vcc - 0.2V or VIN<Vss + 0.2V ICCDR Data Retention Current Vcc=3.0V, /CS>Vcc - 0.2V, VIN>Vcc - 0.2V or VIN<Vss + 0.2V

tCDR Chip Deselect to Data

Retention Time tR Operating Recovery Time Timing Diagram tRC(2) Notes

1. Typical values are under the condition of TA = 25°C.

2. tRC is read cycle time.

DATA RETENTION TIMING DIAGRAM

VCC

4.5V

Parameter Test Condition Min Typ Max Unit

0~70°C

-25~85°C or

- 0.5 5 uA

- 0.5 8 uA

-40~85°C

See Data Retention 0 - - ns

- - ns

DATA RETENTION MODE

tCDR tR

VDR

CS>VCC-0.2V

CS

Rev 04 / Apr. 2001

8

HY62CT08081E Series

PACKAGE INFORMATION

28pin 600mil Dual In-Line Package(Blank)

•

1.467(37.262)

1.447(36.754)

0.090(2.286)

0.070(1.778)

0.100(2.54)BSC

0.065(1.650)

0.050(1.270)

0.021(0.533)

0.015(0.381)

28pin 330mil Small O utline Package(FW)

0.155(3.937)

0.145(3.683)

0.035(0.889)

0.020(0.508)

0.140(3.556)

0.120(3.048)

UNIT : INCH(mm)

0.600(15.240)BSC

0.550(13.970)

0.530(13.462)

3 deg 11 deg

0.014(0.356)

0.008(0.200)

MAX. MIN.

0.346(8.788)

0.338(8.585)

0.728(18.491)

0.720(18.288)

0.050(1.270)BSC 0.020(0.508)

0.014(0.356)

UNIT : INCH(mm)

0.480(12.192)

0.460(11.684)

0.110(2.794)

0.094(2.388)

0.014(0.356)

0.002(0.051)

0.050(1.270)

0.030(0.762)

MAX MIN.

0.012(0.305)

0.008(0.203)

Rev 04 / Apr. 2001

9

HY62CT08081E Series

0.008(0.20)

0.002(0.05)

28pin 8x13.4mm Thin Small Outline Package Standard(T)

0.027(0.7)

0.012(0.3)

0.468(11.9)

0.460(11.7)

0.536(13.6)

0.520(13.2)

0.008(0.2)

0.004(0.1)

UNIT : INCH(mm)

0.319(8.1)

0.311(7.9)

0.022(0.55 BSC)

MAX. MIN.

0.040(1.02)

0.036(0.91)

Rev 04 / Apr. 2001

10

HY62CT08081E Series

MARKING INFORMATION

Package Marking Example

PDIP

SOP

TSOP-I

h y n i x y y

H Y 6 2 C T 0 8 1 E c

K O R E A x x x x x

h y n i x y y

H Y 6 2 C T 0 8 1 E c

K O R E A

h y n i x y

H Y 6 2 C T 0 8 1 E

K O R E A

Index

w w p

s s t

x x x

w w p

s s t

y w w p

c s s t

• hynix : hynix Logo

• KOREA : Origin Country

•

HY62CT081E

• yy : Year ( ex : 00 = year 2000, 01 = year 2001 )

• ww : Work Week ( ex : 12 = ww12 )

• p : Process Code

• c : Power Consumption

• ss : Speed

• t : Temperature

• xxxxxxxx : Lot Number

Note

- Capital Letter : Fixed Item

- Small Letter : Non-fixed Item ( Except hynix )

: Part Name

- HY62CT081E : HY62CT08081E

- L : Low Power

- D : Low Low Power

- 55 : 55ns

- 70 : 70ns

- C : Commercial ( 0 ~ 70 °C )

- E : Extended ( -25 ~ 85 °C )

- I : Industrial ( -40 ~ 85 °C )

Rev 04 / Apr. 2001

11