Page 1
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
Revision History
Rev. No. History Issue Date Remark
1.0 Initial issue Jan.19,2005
2.0 Add green code in order information May.12,2005
1 Rev. 2.0
MCU reserves the right to change product or specification without notice.
Page 2
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
GENERAL DESCRIPTION
The HM62256 is a high performance, high speed and super low power CMOS Static Random
Access Memory organized as 32,768 words by 8bits and operates for a single 4.5 to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high speed, super low power features
and maximum access time of 55/70ns in 5.0V operation. Easy memory expansion is provided by an
active LOW chip enable (/CE) and active LOW output enable (/OE).
The HM62256 has an automatic power down feature, reducing the power consumption significantly
when chip is deselected. The HM62256 is available in JEDEC standard 28-pin SOP (330 mil) and PDIP
(600 mil) packages.
FEATURES
Wide operation voltage : 4.5 ~ 5.5V
Ultra low power consumption : 2mA＠1MHz (Max.) , Vcc=5.0V.
1.0 uA (Typ.) CMOS standby current
High speed access time : 55/70ns.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE and /OE options.
PRODUCT FAMILY
Product Family Operating Temp. Vcc Range Speed (ns)
HM62256 0~70oC 4.5~5.5V 55/70
Standby Current(Typ.)
I
(Vcc = 5.0V)
CCSB1
1.0 uA
Package Type
28 SOP
28 PDIP
2 Rev. 2.0
MCU reserves the right to change product or specification without notice.
Page 3
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTIONS
Name Type Function
A0 – A14
/CE
/WE
/OE
DQ0~DQ7
Input Address inputs for selecting one of the 32,768 x 8 bit words in the RAM
/CE is active LOW. Chip enable must be active when data read from or write
to the device. If chip enable is not active, the device is deselected and in a
Input
standby power mode. The DQ pins will be in high impedance state when the
device is deselected.
The Write enable input is active LOW. It controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
Input
be present on the DQ pins, when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
Input
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the
I/O
RAM.
Vcc
Gnd
3 Rev. 2.0
Power Power Supply
Power Ground
MCU reserves the right to change product or specification without notice.
Page 4
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
TRUTH TABLE
Mode /CE /WE /OE DQ0~7 Vcc Current
Standby H X X High Z
Output Disabled L H H High Z ICC
Read L H L D
Write L L X DIN I
I
OUT
I
CCSB
, I
CC
CC
CCSB1
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Rating Unit
V
TERM
T
BIAS
T
STG
PT
I
OUT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 V
Temperature Under Bias -40 to +125
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
O
C
O
C
rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Ambient Temperature
o
0~70
C
4.5~5.5V
Vcc
CAPACITANCE
Symbol Parameter Conduction MAX. Unit
CIN
CDQ
1. This parameter is guaranteed, and not 100% tested.
4 Rev. 2.0
Input Capacitance VIN=0V 6 pF
Input/Output Capacitance VI/O=0V 8 pF
MCU reserves the right to change product or specification without notice.
(1)
(TA=25℃,f=1.0MHz)
Page 5
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
DC ELECTRICAL CHARACTERISTICS ( TA = 0
Name Parameter Test Condition MIN TYP
o
~70oC, Vcc = 5.0V)
(1)
MAX Unit
Guaranteed Input Low
VIL
VIH
IIL
IOL
VOL
VOH
ICC
I
CCSB
I
CCSB1
Voltage
Guaranteed Input High
Voltage
Input Leakage Current VCC=MAX, VIN=0 to VCC
Output Leakage Current
Output Low Voltage VCC=MAX, I
Output High Voltage VCC=MIN, I
Operating Power Supply
Current
TTL Standby Supply /CE=VIH, IDQ=0mA,
CMOS Standby Current
(2)
(2)
1. Typical characteristics are at TA = 25
Vcc=5.0V
Vcc=5.0V
VCC=MAX, /CE=VIN, or
/OE=V
/CE=VIL, IDQ=0mA,
F=F
/CE≧VCC-0.2V, VIN≧
VCC-0.2V or VIN≦0.2V,
o
C.
, VIO=0V to VCC
IN
= 1mA
OL
= -1mA
OH
=1/ tRC
MAX
-0.5 0.8
2.5 Vcc+0.2
-1 1
-1 1
0.4
2.2
20
1
1.0 10
V
V
uA
uA
V
V
mA
mA
uA
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
DATA RETENTION CHARACTERISTICS ( TA = 0
Name Parameter Test Condition MIN TYP
for Data Retention
V
VDR
CC
Data Retention Current
I
CCDR
Chip Deselect to Data
T
CDR
Retention Time
tR Operation Recovery Time
1. TA = 25
2. t
o
C.
Read Cycle Time.
RC= .
/CE ≧ V
V
-0.2V or VIN≦0.2V
CC
/CE≧V
V
IN≧VCC
Retention Waveform
-0.2V, VIN≧
CC
-0.2V, VCC=2V
CC
-0.2V or VIN≦0.2V
Refer to
o
~70oC)
(1)
MAX Unit
1.5 V
0.5 3 uA
0 ns
(2)
t
RC
ns
5 Rev. 2.0
MCU reserves the right to change product or specification without notice.
Page 6
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled )
Data Retention Mode
V
Vcc
t
CDR
VIH
CE >= VCC - 0.2V
CE
AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS
>= 1.5V
DR
t
R
VIH
Input Pulse Levels Vcc/0V
Input Rise and Fall Times 5ns
Input and Output Timing
0.5Vcc
Reference Level
WAVEFORMS INPUTS OUTPUTS
MUST BE STEADY MUST BE STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON’T CARE ANY
CHANGE
PERMITTED
DOES NOT APPLY
WILL BE CHANGE FROM H
TO L
WILL BE CHANGE FROM L
TO H
CHANGE STATE
UNKNOWN
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
AC TEST LOADS AND WAVEFORMS
FIGURE 1A
FIGURE 1B
6 Rev. 2.0
MCU reserves the right to change product or specification without notice.
Page 7
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
AC ELECTRICAL CHARACTERISTICS ( TA = 0
< READ CYCLE >
o
~70oC, Vcc = 5.0V )
Name
t
t
AVA X
t
t
AV QV
t
t
ELQV
t
t
GLQV
t
t
ELQX
t
t
GLQX
t
t
EHQZ
t
t
GHQZ
t
t
AXOX
Symbol Description
Read Cycle Time 55 70
RC
Address Access Time 55 70
AA
Chip Select Access Time 55 70
ACE
Output Enable to Output
OE
Valid
Chip Select to Output Low Z 10 10
CLZ
Output Enable to Output in
OLZ
Low Z
Chip Deselect to Output in
CHZ
High Z
Output Disable to Output in
OHZ
High Z
Address Change to Out
OH
Disable
-55 -70 JEDEC
MIN MAX MIN MAX
30 50
5 5
0 35 0 35
0 30 0 30
10 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
ADDRESS
t
t
OH
D
OUT
7 Rev. 2.0
MCU reserves the right to change product or specification without notice.
AA
t
OH
Page 8
READ CYCLE2
READ CYCLE3
ADDRESS
(1,3,4)
(1,4)
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
t
RC
t
AA
t
OH
OE
t
t
OHZ
CHZ
(1,5)
(5)
t
OE
t
t
CLZ
(5)
OLZ
t
CE
CE
D
OUT
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = V
IL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input
pulse levels of 0V to VCC and output loading specified in Figure 1A.
6. Transition is measured ±500mV from steady state with C
= 5pF as shown in Figure 1B. The parameter is
L
guaranteed but not 100% tested.
8 Rev. 2.0
MCU reserves the right to change product or specification without notice.
Page 9
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
AC ELECTRICAL CHARACTERISTICS ( TA = 0
< WRITE CYCLE >
o
~70oC, Vcc = 5.0V )
Name
t
t
t
t
t
AVA X
t
E1LWH
t
t
AV WL
t
t
AV WH
t
WLWH
t
t
WHAX
t
t
WLQZ
t
t
DVWH
t
t
WHDX
t
t
GHQZ
t
WHOX
Symbol Description
Write Cycle Time 55 70
WC
Chip Select to End of Write 55 70
CW
Address Setup Time 0 0
AS
Address Valid to End of Write 55 70
AW
Write Pulse Width 40 50
WP
Write Recovery Time 0 0
WR
Write to Output in High Z 25 35
WHZ
Data to Write Time Overlap 20 30
DW
Data Hold for Write End 0 0
DH
Output Disable to Output in
OHZ
High Z
End of Write to Output Active 5 5
OW
-55 -70 JEDEC
MIN MAX MIN MAX
0 30 0 30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (Write Enable Controlled)
9 Rev. 2.0
MCU reserves the right to change product or specification without notice.
Page 10
High Speed Super Low Power SRAM
32K-Word By 8 Bit HM62256
WRITE CYCLE2 (Chip Enable Controlled)
NOTES:
1. /WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active
to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold
timing should be referenced to the second transition edge of the signal that terminates the write.
3. T
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output
6. It’s recommended to keep /OE at high (/OE = VIH ) as /WE Controlled WRITE CYCLE.
7. D
8. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase
9. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse
is measured from the earlier of /CE or /WE going high at the end of write cycle.
WR
must not be applied.
remain in a high impedance state.
is the read data of next address.
OUT
to the outputs must not be applied to them.
levels of 0V to VCC and output loading specified in Figure 1A.
10. Transition is measured ±500mV from steady state with C
guaranteed but not 100% tested.
11. T
is measured from the later of /CE going low to the end of write.
CW
10 Rev. 2.0
MCU reserves the right to change product or specification without notice.
= 5pF as shown in Figure 1B. The parameter is
L
Page 11
High Speed Super Low Power SRAM
ORDER INFORMATION
32K-Word By 8 Bit
HM62256
11 Rev. 2.0
MCU reserves the right to change product or specification without notice.
Page 12
Page 13
Loading...