Page 1
®
IS61C256AH
ISSI
32K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2002
FEATURES
• High-speed access time: 10, 12, 15, 20 ns
• Low active power: 400 mW (typical)
• Low standby power
— 250 µW (typical) CMOS standby
— 55 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
DESCRIPTION
The
ISSI
IS61C256AH is a very high-speed, low power,
32,768 word by 8-bit static RAMs. They are fabricated using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 10 ns maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C256AH is pin compatible with other 32K x 8
SRAMs and are available in 28-pin SOJ and TSOP (Type I)
packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
CE
OE
WE
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
32K X 8
MEMORY ARRAY
COLUMN I/O
ISSI reserves the right to make changes this specification herein and it products at any time without notice. ISSI assumes no responsibility or liability arising out of the application or use of any information,
product or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
© Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — www.issi.com —
SR020-1P
07/17/2002
1-800-379-4774
1
Page 2
IS61C256AH
®
ISSI
PIN CONFIGURATION
28-Pin SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
Vcc Power
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
TRUTH TABLE
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
CECE
OEOE
CE
OE I/O Operation Vcc Current
CECE
OEOE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 ° C
PT Power Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
SR020-1P
07/17/02
Page 3
IS61C256AH
ISSI
OPERATING RANGE
Range Ambient Temperature Speed VCC
Commercial 0°C to +70°C -10, -12 5V ± 5%
-15, -20 5V ± 10%
Industrial –40°C to +85°C -1 2 5V ± 5%
-15, -20 5V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage
(1)
–0.5 0.8 V
®
ILI Input Leakage GND - VIN - VCC Com. –5 5 µA
Ind. –10 10
ILO Output Leakage GND - VOUT - VCC, Com. –5 5 µA
Outputs Disabled Ind. –10 10
Note:
IL = –3.0V for pulse width less than 10 ns.
1. V
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 165 — 155 — 145 — 135 m A
Supply Current IOUT = 0 mA, f = fMAX Ind. — — — 165 — 155 — 145
ISB1 TTL Standby Current VCC = Max., Co m . — 2 5 — 2 5 — 25 — 25 m A
(TTL Inputs) VIN = VIH or VIL Ind. — — — 30 — 30 — 30
CE • VIH, f = 0
ISB2 CMOS Standby VCC = Max., Co m. — 2 — 2 — 2 — 2 mA
Current (CMOS Inputs) CE • VCC – 0.2V, Ind. — — — 10 — 10 — 10
VIN • VCC – 0.2V, or
VIN - 0.2V, f = 0
(1)
(Over Operating Range)
-10 -12 -15 -20
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. — www.issi.com —
SR020-1P
07/17/02
1-800-379-4774
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Page 4
IS61C256AH
®
ISSI
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Output Capacitance VOUT = 0V 10 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
READ CYCLE SWITCHING CHARACTERISTICS
A = 25°C, f = 1 MHz, Vcc = 5.0V.
(1)
(Over Operating Range)
-10 ns -12 ns -15 ns -20 ns
Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 10 — 12 — 15 — 2 0 — ns
tAA Address Access Time — 10 — 12 — 15 — 20 ns
tOHA Output Hold Time 2 — 2 — 2 — 2 — ns
tACE CE Access Time — 10 — 12 — 1 5 — 20 ns
tDOE OE Access Time — 5 — 5 — 7 — 8 ns
(2)
tLZOE
tHZOE
tLZCE
tHZCE
(3)
tPU
(3)
tPD
(2)
(2)
(2)
OE to Low-Z Output 0 — 0 — 0 — 0 — ns
OE to High-Z Output — 5 — 6 — 7 — 9 ns
CE to Low-Z Output 2 — 3 — 3 — 3 — ns
CE to High-Z Output — 5 — 7 — 8 — 9 ns
CE to Power-Up 0 — 0 — 0 — 0 — ns
CE to Power-Down — 10 — 1 2 — 15 — 18 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
4
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Page 5
IS61C256AH
AC TEST LOADS
®
ISSI
5V
OUTPUT
30 pF
Including
jig and
scope
Figure 1
AC WAVEFORMS
READ CYCLE NO. 1
ADDRESS
D
OUT
480 Ω
255 Ω
(1,2)
PREVIOUS DATA VALID
t OHA
t AA
t RC
OUTPUT
5V
Including
DATA VALID
5 pF
jig and
scope
Figure 2
480 Ω
255 Ω
t OHA
READ CYCLE NO. 2
(1,3)
t
ADDRESS
t
AA
OE
t
DOE
t
CE
t
LZCE
OUT
D
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = V
3. Address is valid prior to or coincident with CE LOW transitions.
HIGH-Z
LZOE
t
ACE
IL.
RC
DATA VALID
t
HZCE
t
t
OHA
HZOE
READ1.eps
CE_RD2.eps
Integrated Silicon Solution, Inc. — www.issi.com —
SR020-1P
07/17/02
1-800-379-4774
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Page 6
IS61C256AH
®
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-10 ns -12 ns -15 ns -20 ns
Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 10 — 12 — 1 5 — 20 — ns
tSCE CE to Write End 9 — 10 — 10 — 13 — ns
tAW Address Setup Time 9 — 10 — 12 — 15 — ns
to Write End
tHA Address Hold 0 — 0 — 0 — 0 — ns
from Write End
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWE1 WE Pulse Width (OE LOW) 8 — 8 — 10 — 13 — ns
tPWE2 WE Pulse Width (OE HIGH) 6.5 — 7 — 8 — 10 — ns
tSD Data Setup to Write End 7 — 7 — 9 — 10 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
(2)
tHZWE
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
WE LOW to High-Z Output — 6 — 6 — 7 — 8 ns
(2)
WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns
AC WAVEFORMS
WRITE CYCLE NO. 1 (
ADDRESS
t
CE
WE
OUT
D
DIN
6
DATA UNDEFINED
WEWE
WE Controlled)
WEWE
SA
(1,2)
t
WC
VALID ADDRESS
t
t
HZWE
SCE
t
AW
t
PWE1
t
PWE2
HIGH-Z
t
SD
DATAIN VALID
t
HA
t
LZWE
t
HD
Integrated Silicon Solution, Inc. — www.issi.com —
CE_WR1.eps
1-800-379-4774
SR020-1P
07/17/02
Page 7
IS61C256AH
®
ISSI
WRITE CYCLE NO. 2
ADDRESS
OE
LOW
t
SA
D
CE
WE
OUT
DIN
(OE is HIGH During Write Cycle)
t
VALID ADDRESS
t
AW
t
t
HZWE
DATA UNDEFINED
WC
PWE1
(1,2)
HIGH-Z
t
SD
DATAIN VALID
t
HA
t
LZWE
t
HD
CE_WR2.eps
WRITE CYCLE NO. 3
ADDRESS
OE
CE
LOW
LOW
(OE is LOW During Write Cycle)
VALID ADDRESS
t
AW
t
t
(1)
WC
PWE2
t
HA
WE
t
SA
OUT
D
DATA UNDEFINED
DIN
t
HZWE
HIGH-Z
t
SD
DATAIN VALID
t
LZWE
t
HD
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE • V
IH.
Integrated Silicon Solution, Inc. — www.issi.com —
SR020-1P
07/17/02
1-800-379-4774
7
Page 8
IS61C256AH
®
ISSI
ORDERING INFORMATION: IS61C256AH
Commercial Range: 0°C to +70°C
Speed (ns) Order Part Number Package
10 IS61C256AH-10J 300-mil Plastic SOJ
IS61C256AH-10T TSOP (Type 1)
12 IS61C256AH-12J 300-mil Plastic SOJ
IS61C256AH-12T TSOP (Type 1)
15 IS61C256AH-15J 300-mil Plastic SOJ
IS61C256AH-15T TSOP (Type 1)
20 IS61C256AH-20J 300-mil Plastic SOJ
IS61C256AH-20T TSOP (Type 1)
ORDERING INFORMATION: IS61C256AH
Industrial Range: –40°C to +85°C
Speed (ns) Order Part Number Package
12 IS61C256AH-12JI 300-mil Plastic SOJ
IS61C256AH-12TI TSOP (Type 1)
15 IS61C256AH-15JI 300-mil Plastic SOJ
IS61C256AH-15TI TSOP (Type 1)
20 IS61C256AH-20JI 300-mil Plastic SOJ
IS61C256AH-20TI TSOP (Type 1)
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
SR020-1P
07/17/02
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