Datasheet 5962P0153301TXC, 5962P0153301QXC, 5962L0153301TXC, 5962-0153301TXC, 5962-0153301QXC Datasheet (UTMC)

FEATURES

q 25ns maximum (3.3 volt supply) address access time
q MCM contains four (4) 512K x 8 industry-standard

asynchronous SRAMs; the control architecture allows
operation as 8, 16, 24, or 32-bit data width

q TTL compatible inputs and output levels, three-state

bidirectional data bus

q Typical radiation performance

- Total dose: 50krads

- SEL Immune >80 MeV-cm2/mg

- LETTH(0.25) = >10 MeV-cm2/mg

- Saturated Cross Section cm2 per bit, 5.0E-9

- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion

q Packaging options:

- 68-lead dual cavity ceramic quad flatpack (CQFP) ­(weight 7.37 grams)

q Standard Microcircuit Drawing 5962-01533

- QML T and Q compliant part

INTRODUCTION

The QCOTSTM UT8Q512K32 Quantified Commercial
Off-the-Shelf product is a high-performance 2M byte
(16Mbit) CMOS static RAM multi-chip module (MCM),
organized as four individual 524,288 x 8 bit SRAMs with a
common output enable. Memory expansion is provided by
an active LOW chip enable (En), an active LOW output
enable (G), and three-state drivers. This device has a power­down feature that reduces power consumption by more than
90% when deselected .

Writing to each memory is accomplished by taking the chip
enable (En) input LOW and write enable (Wn) inputs LOW.
Data on the I/O pins is then written into the location
specified on the address pins (A0 through A18). Reading

from the device is accomplished by taking the chip enable
(En) and output enable (G) LOW while forcing write enable
(Wn) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear
on the I/O pins.

The input/output pins are placed in a high impedance state
when the device is deselected (En HIGH), the outputs are
disabled (G HIGH), or during a write operation (En LOW
and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by
making Wn along with En a common input to any
combination of the discrete memory die.

Figure 1. UT8Q512K32 SRAM Block Diagram

512K x 8

512K x 8 512K x 8 512K x 8

DQ(31:24)

or

DQ3(7:0)

DQ(23:16)

or

DQ2(7:0)

DQ(15:3)

or

DQ1(7:0)

DQ(7:0)

or

DQ0(7:0)

G

A(18:0)

W

3

E

3

E

2

E

1

E

0

W

2

W

1

W

0

Standard Products

QCOTS

TM

UT8Q512K32 16Megabit SRAM MCM

Data Sheet

June, 2003

2

PIN NAMES

DEVICE OPERATION

Each die in the UT8Q512K32 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes I

DD

to rise to its active value, and decodes the 19 address

inputs to each memory die by selecting the 2,048,000 byte of
memory. Wn controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of Wn greater than V

IH

(min) with En and G less

than V

IL

(max) defines a read cycle. Read access time is

measured from the latter of device enable, output enable, or valid
address to valid data output.

SRAM read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQn(7:0)
after the specified t

AVQV

is satisfied. Outputs remain active

throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (t

AVAV

).

SRAM read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t

ETQV

is satisfied, the eight-bit

word addressed by A(18:0) is accessed and appears at the data
outputs DQn(7:0).

SRAM read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
t

GLQV

unless t

AVQV

or t

ETQV

have not been satisfied.

A(18:0) Address Wn WriteEnable

DQ(7:0) Data Input/Output G Output Enable

En

Device Enable

V

DD

Power

V

SS

Ground

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Top View

DQ0(0)
DQ1(0)
DQ2(0)
DQ3(0)
DQ4(0)
DQ5(0)
DQ6(0)
DQ7(0)

V

SS

DQ0(1)
DQ1(1)

DQ2(1)
DQ3(1)
DQ4(1)
DQ5(1)
DQ6(1)
DQ7(1)

DQ0(2)
DQ1(2)
DQ2(2)
DQ3(2)
DQ4(2)
DQ5(2)
DQ6(2)
DQ7(2)

V

SS

DQ0(3)
DQ1(3)
DQ2(3)
DQ3(3)
DQ4(3)
DQ5(3)
DQ6(3)
DQ7(3)

NC

A0A1A2A3A4A5E2

V

SS

E3W0A6A7A8

A9

A10

V

DD

V

DD

A11

A12

A13

A14

A15

A16

E0GE1

A17

W1W2W3

A18

NC

NC

Figure 2. 25ns SRAM Pinout (68)

G Wn En I/O Mode Mode

X

1

X 1 3-state Standby

X 0 0 Data in Write

1 1 0 3-state

Read

2

0 1 0 Data out Read

3

WRITE CYCLE

A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance

state when either G is greater than VIH(min), or when Wn is less
than VIL(max).

Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by t

WLWH

when the write is

initiated by Wn, and by t

ETWH

when the write is initiated by En.

Unless the outputs have been previously placed in the high­impedance state by G, the user must wait t

WLQZ

before applying

data to the eight bidirectional pins DQn(7:0) to avoid bus
contention.

Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by t

WLEF

when the write is

initiated by Wn, and by t

ETEF

when the write is initiated by the

En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait t

WLQZ

before applying data to the eight

bidirectional pins DQn(7:0) to avoid bus contention.

TYPICAL RADIATION HARDNESS

The UT8Q512K32 SRAM incorporates features which allow
operation in a limited radiation environment.

Table 2. Typical Radiation Hardness

Design Specifications

1

Notes:

1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.

2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.

Total Dose 50 krad(Si) nominal

Heavy Ion
Error Rate

2

<1E-8 Errors/Bit-Day

4

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3. Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD

DC supply voltage -0.5 to 4.6V

V

I/O

Voltage on any pin -0.5 to 4.6V

T

STG

Storage temperature -65 to +150°C

P

D

Maximum power dissipation 1.0W (per byte)

T

J Maximum junction temperature

2

+150°C

Θ

JC

Thermal resistance, junction-to-case

3

10°C/W

I

I

DC input current

±10 mA

SYMBOL PARAMETER LIMITS

V

DD

Positive supply voltage 3.0 to 3.6V

T

C

Case temperature range -40 to +125°C

V

IN

DC input voltage 0V to V

DD

5

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(-40°C to +125°C) (VDD = 3.3V + 0.3)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 101 9.

1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

V

IH

High-level input voltage (CMOS) 2.0 V

V

IL

Low-level input voltage (CMOS) 0.8 V

V

OL1

Low-level output voltage IOL = 8mA, VDD =3.0V

0.4

V

V

OL2

Low-level output voltage IOL = 200µA,VDD =3.0V 0.08 V

V

OH1

High-level output voltage IOH = -4mA,VDD =3.0V 2.4 V

V

OH2

High-level output voltage IOH = -200µA,VDD =3.0V VDD-0.10 V

C

IN

1

Input capacitance ƒ = 1MHz @ 0V 32 pF

C

IO

1

Bidirectional I/O capacitance ƒ = 1MHz @ 0V 16 pF

I

IN

Input leakage current VSS < VIN < V

DD, VDD

= VDD (max) -2 2 µA

I

OZ

Three-state output leakage current 0V < VO < V

DD

VDD = VDD (max)
G = VDD (max)

-2 2 µA

I

OS

2, 3

Short-circuit output current 0V < VO < V

DD

-90 90 mA

IDD(OP)

Supply current operating
@ 1MHz
(per byte)

Inputs: VIL = 0.8V,
VIH = 2.0V
I

OUT

= 0mA

VDD = VDD (max)

125 mA

I

DD1

(OP) Supply current operating

@40MHz

(per byte)

Inputs: VIL = 0.8V,
VIH = 2.0V
I

OUT

= 0mA

VDD = VDD (max)

180 mA

I

DD2

(SB) Nominal standby supply current

@0MHz

(per byte)

Inputs: VIL = V

SS

I

OUT

= 0mA

En = V

DD

- 0.5, V

DD

= VDD (max)

VIH = VDD - 0.5V

6

40

mA

mA

-40°C and
25°C

+125°C

6

AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*

(-40°C to +125°C) (VDD = 3. 3V + 0.3)

Notes: * Post-radiation performance guaranteed at 25 °C per MIL-STD-883 Method 1019.

1. Functional test.

2. Three-state is defined as a 300mV change from steady-state output voltage.

3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.

4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.

SYMBOL PARAMETER MIN MAX UNIT

t

AVAV

1

Read cycle time 25 ns

t

AVQV

Read access time 25 ns

t

AXQX

2

Output hold time 3 ns

t

GLQX

2

G-controlled Output Enable time 3 ns

t

GLQV

G-controlled Output Enable time (Read Cycle 3) 10 ns

t

GHQZ

2

G-controlled output three-state time 10 ns

t

ETQX

2,3

En-controlled Output Enable time 3 ns

t

ETQV

3

En-controlled access time 25 ns

t

EFQZ

1,2,4

En-controlled output three-state time 10 ns

{
{

}

}

V

LOAD

+ 300mV

V

LOAD

- 300mV

V

LOAD

VH - 300mV

VL + 300mV

Active to High Z LevelsHigh Z to Active Levels

Figure 3. 3-Volt SRAM Loading

7

Assumptions:

1. En and G < VIL (max) and Wn > VIH (min)

A(18:0)

DQn(7:0)

Figure 4a. SRAM Read Cycle 1: Address Access

t

AVAV

t

AVQV

t

AXQX

Previous Valid Data

Valid Data

Assumptions:

1. G < VIL (max) and Wn > VIH (min)

A(18:0)

Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access

En

DATA VALID

t

EFQZ

t

ETQX

t

ETQV

DQn(7:0)

Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access

A(18:0)

DQn(7:0)

G

t

GHQZ

Assumptions:

1. En < VIL (max) and W n > VIH (min)

t

GLQV

t

GLQX

t

AVQV

DATA VALID

8

AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*

(-40°C to +125°C) (VDD = 3. 3V + 0.3)

Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 101 9.

1. Functional test performed with outputs disabled (G high).

2. Three-state is defined as 300mV change from steady-state output voltage.

SYMBOL PARAMETER MIN MAX UNIT

t

AVAV

1

Write cycle time 25 ns

t

ETWH

Device Enable to end of write 20 ns

t

AVET

Address setup time for write (En - controlled) 1 ns

t

AVWL

Address setup time for write (Wn - controlled) 0 ns

t

WLWH

Write pulse width 20 ns

t

WHAX

Address hold time for write (Wn - controlled) 2 ns

t

EFAX

Address hold time for Device Enable (En - controlled) 2 ns

t

WLQZ

2

Wn- controlled three-state time 10 ns

t

WHQX

2

Wn - controlled Output Enable time 5 ns

t

ETEF

Device Enable pulse width (En - controlled) 20 ns

t

DVWH

Data setup time 15 ns

t

WHDX

2

Data hold time 2 ns

t

WLEF

Device Enable controlled write pulse width 20 ns

t

DVEF

2

Data setup time 15 ns

t

EFDX

Data hold time 2 ns

t

AVWH

Address valid to end of write 20 ns

t

WHWL

1

Write disable time 5 ns

9

Assumptions:

1. G < VIL (max). If G > VIH (min) then Qn(8:0) will be
in three-state for the entire cycle.

2. G high for t

AVAV

cycle.

Wn

t

AVWL

Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access

A(18:0)

Qn(7:0)

En

t

AVAV

2

Dn(7:0)

APPLIED DATA

t

DVWH

t

WHDX

t

ETWH

t

WLWH

t

WHAX

t

WHQX

t

WLQZ

t

AVWH

t

WHWL

10

t

EFDX

Assumptions & Notes:

1. G < VIL (max). If G > V IH (min) then Qn(7:0) will be in three-state for the entire cycle.

2. Either En scenario above can occur.

3. G high for t

AVAV

cycle.

A(18:0)

Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access

Wn

En

Dn(7:0)

APPLIED DATA

En

Qn(7:0)

t

WLQZ

t

ETEF

t

WLEF

t

DVEF

t

AVAV

3

t

AVET

t

AVET

t

ETEF

t

EFAX

t

EFAX

or

Notes:

1. 50pF including scope probe and test socket capacitance.

2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = VDD/2).

90%

Figure 6. AC Test Loads and Input Waveforms

Input Pulses

10%

< 5ns

< 5ns

V

LOAD

= 1.55

300 ohms

50pF

CMOS

0.5V

90%VDD-0.05V

10%

11

DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)

(1 Second Data Rentention Test)

Notes:

1. En = V

DD

- .2V, all other inputs = VDR or VSS.

2. Data retention current (I

DDR

) Tc = 25oC.

3. Not guaranteed or tested.

4. VDR = T=-40oC and 125oC.

DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)

(10 Second Data Retention Test, TC=-40oC and +125oC)

Notes:

1. Performed at VDD (min) and VDD (max).

2. En = VSS, all other inputs = VDR or VSS.

3. Not guaranteed or tested.

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

V

DR

VDD for data retention 2.0 -- V

I

DDR

1,2

Data retention current (per byte) -- 2.0 mA

t

EFR

1,3

Chip select to data retention time 0 ns

t

R

1,3

Operation recovery time t

AVAV

ns

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

V

DD

1

VDD for data retention 3.0 3.6 V

t

EFR

2, 3

Chip select to data retention time 0 ns

t

R

2, 3

Operation recovery time t

AVAV

ns

V

DD

DATA RETENTION MODE

t

R

50%

50%

VDR > 2.0V

Figure 7. Low VDD Data Retention Waveform

t

EFR

En

12

PACKAGING

Figure 8. 68-pin Ceramic FLATPACK

Notes:

1. Package shipped with non-conductive
strip (NCS). Leads are not trimmed.

2. Total weight approx. 7.37g.

13

ORDERING INFORMATION
512K32 16Megabit SRAM MCM:

Notes:

1. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY.

2. Extended Industrial Temperature Range Flow per UTMC Manufacturing Flows document. Devices are tested at -40oC to +125oC. Radiation neither
tested nor guaranteed. Gold lead finish only.

Device Type:

- = 25ns access, 3.3V operation

Package Type:
(S) = 68-lead dual cavity CQFP

Screening:
(P) = Prototype flow

(W) = Extended Industrial Temperature Range Flow (-40oC to +125oC)

Lead Finish:
(C) = Gold

UT8Q512K32 -* * * *

Aeroflex UTMC Core Part Number

14

512K32 16Megabit SRAM MCM: SMD

5962 - 01533 **

* * *

Notes:

1. Total dose radiation must be specified when ordering. Gold lead finish only.

2. Only Extended Industrial Temperature -40C to +125C. No military temp. test available.

Federal Stock Class Designator: No Options

Total Dose
(-) = none
(D) = 1E4 (10krad(Si))
(L) = 5E4 (50krad(Si)) (contact factory)
(P) = 3E4 (30krad(Si)) (contact factory)

Drawing Number: 01533

Device Type
01 = 25ns access time, 3.3V operation, Extended Industrial Temp (-40oC to +125oC)

Class Designator:
(T) = QML Class T
(Q) = QML Class Q

Case Outline:
(X) = 68-lead dual cavity CQFP

Lead Finish:
(C) = Gold