Datasheet 5962P0153201TYX, 5962P0153201TYA, 5962P0153201QYX, 5962P0153201QYC, 5962P0153201QYA Datasheet (UTMC)

1

FEATURES

q 25ns maximum (3.3 volt supply) address access time
q Dual cavity package contains two (2) 512K x 8 industry-

standard asynchronous SRAMs; the control architecture
allows operation as an 8-bit data width

q TTL compatible inputs and output levels, three-state

bidirectional data bus

q Typical radiation performance

- Total dose: 50krad(Si)

- SEL Immune >80 MeV-cm2/mg

- LETTH(0.25) = >10 MeV-cm2/mg

- Saturated Cross Section cm2 per bit, 5. 0E-9

- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion

q Packaging options:

- 44-lead bottom brazed dual CFP (BBTFP) (4.6 grams)

q Standard Microcircuit Drawing 5962-01532

- QML T and Q compliant part

INTRODUCTION

The QCOTSTM UT8Q1024K8 Quantified Commercial Off-the­Shelf product is a high-performance 1M byte (8Mbit) CMOS
static RAM built with two individual 524,288 x 8 bit SRAMs
with a common output enable. Memory access and control is
provided by an active LOW chip enable (En), an active LOW
output enable (G). This device has a power-down feature that
reduces power consumption by more than 90% when deselected.

Writing to each memory is accomplished by taking one of the
chip enable (En) inputs LOW and write enable (Wn) inputs
LOW. Data on the I/O pins is then written into the location
specified on the address pins (A0 through A18). Reading from

the device is accomplished by taking one of the chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
Only one SRAM can be read or written at a time.

The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).

Figure 1. UT8Q 1024K8 SRAM Block Diagram

512K x 8 512K x 8

DQ(7:0)

G

A(18:0)

E

1

E

0

W

1

W

0

Standard Products

QCOTS

TM

UT8Q1024K8 SRAM

Data Sheet

January, 2003

2

PIN NAMES

Notes:

1. To avoid bus contention, on the DQ(7:0) bus, only one En can be driven low
simultaneously while G is low.

DEVICE OPERATION

Each die in the UT8Q1024K8 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes I

DD

to rise to its active value, and decodes the 19 address

inputs to each memory die. Wn controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of Wn greater than V

IH

(min) with En and G less

than V

IL

(max) defines a read cycle. Read access time is

measured from the latter of device enable, output enable, or valid
address to valid data output.

SRAM Read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQ(7:0) after
the specified t

AVQV

is satisfied. Outputs remain active

throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (t

AVAV

).

SRAM Read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t

ETQV

is satisfied, the eight-bit

word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).

SRAM Read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
t

GLQV

unless t

AVQV

or t

ETQV

have not been satisfied.

A(18:0) Address

DQ(7:0) Data Input/Output

En Device Enable

Wn WriteEnable

G Output Enable

V

DD

Power

V

SS

Ground

Figure 2. 25ns SRAM Pinout (44)

1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23

NC
E2
NC
A18
A17
A16
A15
G
DQ7
DQ6
V

SS

V

DD

DQ5
DQ4
A14
A13
A12
A11
A10
NC
NC
NC

NC
NC

A0
A1
A2
A3
A4

E1
DQ0
DQ1

V

DD

V

SS

DQ2
DQ3

W1

A5
A6
A7
A8
A9

W2

NC

G Wn En I/O Mode Mode

X

1

X 1 3-state Standby

X 0 0 Data in Write

1 1 0 3-state

Read

2

0 1 0 Data out Read

3

WRITE CYCLE

A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance

state when either G is greater than VIH(min), or when Wn is less
than VIL(max).

Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by t

WLWH

when the write is

initiated by Wn, and by t

ETWH

when the write is initiated by En.

Unless the outputs have been previously placed in the high­impedance state by G, the user must wait t

WLQZ

before applying

data to the eight bidirectional pins DQ(7:0) to avoid bus
contention.

Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by t

WLEF

when the write is

initiated by Wn, and by t

ETEF

when the write is initiated by the

En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait t

WLQZ

before applying data to the eight

bidirectional pins DQ(7:0) to avoid bus contention.

TYPICAL RADIATION HARDNESS

The UT8Q 1024K8 SRAM incorporates features which allow
operation in a limited radiation environment.

Table 2. Typical Radiation Hardness

Design Specifications

1

Notes:

1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.

2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.

Total Dose 50 krad(Si) nominal

Heavy Ion
Error Rate

2

<1E-8 Errors/Bit-Day

4

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175 °C during burn-in and steady-static life.

3. Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD

DC supply voltage -0.5 to 4.6V

V

I/O

Voltage on any pin -0.5 to 4.6V

T

STG

Storage temperature -65 to +150 °C

P

D

Maximum power dissipation 1.0W (per byte)

T

J Maximum junction temperature

2

+150°C

Θ

JC Thermal resistance, junction-to-case

3

10°C/W

I

I

DC input current

±10 mA

SYMBOL PARAMETER LIMITS

V

DD

Positive supply voltage 3.0 to 3.6V

T

C

Case temperature range -40 to +125 °C

V

IN

DC input voltage 0V to V

DD

5

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(-40°C to +125°C) (VDD = 3.3V + 0.3)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 101 9.

1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

V

IH

High-level input voltage (CMOS) 2.0 V

V

IL

Low-level input voltage (CMOS) 0.8 V

V

OL1

Low-level output voltage IOL = 8mA, VDD =3.0V

0.4

V

V

OL2

Low-level output voltage IOL = 200µA,VDD =3.0V 0.08 V

V

OH1

High-level output voltage IOH = -4mA,VDD =3.0V 2.4 V

V

OH2

High-level output voltage IOH = -200µA,VDD =3.0V VDD-0.10 V

C

IN

1

Input capacitance ƒ = 1MHz @ 0V 20 pF

C

IO

1

Bidirectional I/O capacitance ƒ = 1MHz @ 0V 24 pF

I

IN

Input leakage current VSS < VIN < V

DD, VDD

= VDD (max) -2 2 µA

I

OZ

Three-state output leakage current 0V < VO < V

DD

VDD = VDD (max)
G = VDD (max)

-2 2 µA

I

OS

2, 3

Short-circuit output current 0V < VO < V

DD

-90 90 mA

IDD(OP)

Supply current operating
@ 1MHz

Inputs: VIL = 0.8V,
VIH = 2.0V
I

OUT

= 0mA

VDD = VDD (max)

150 mA

I

DD1

(OP) Supply current operating

@40MHz

Inputs: VIL = 0.8V,
VIH = 2.0V
I

OUT

= 0mA

VDD = VDD (max)

220 mA

I

DD2

(SB) Nominal standby supply current

@0MHz

Inputs: VIL = V

SS

I

OUT

= 0mA

En = V

DD

- 0.5,

VDD = VDD (max)
VIH = VDD - 0.5V

4

25

mA

mA

-40°C and 25°C

+125°C

6

AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*

(-40°C to +125 °C) (VDD = 3.3V + 0.3)

Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.

1. Functional test.

2. Three-state is defined as a 300mV change from steady-state output voltage.

3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.

4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.

SYMBOL PARAMETER MIN MAX UNIT

t

AVAV

1

Read cycle time 25 ns

t

AVQV

Read access time 25 ns

t

AXQX

2

Output hold time 3 ns

t

GLQX

2

G-controlled Output Enable time 0 ns

t

GLQV

G-controlled Output Enable time (Read Cycle 3) 10 ns

t

GHQZ

2

G-controlled output three-state time 10 ns

t

ETQX

2,3

En-controlled Output Enable time 3 ns

t

ETQV

3

En-controlled access time 25 ns

t

EFQZ

1,2,4

En-controlled output three-state time 10 ns

{
{

}

}

V

LOAD

+ 300mV

V

LOAD

- 300mV

V

LOAD

VH - 300mV

VL + 300mV

Active to High Z LevelsHigh Z to Active Levels

Figure 3. 3-Volt SRAM Loading

7

Assumptions:

1. En and G < VIL (max) and Wn > VIH (min)

A(18:0)

DQ(7:0)

Figure 4a. SRAM Read Cycle 1: Address Access

t

AVAV

t

AVQV

t

AXQX

Previous Valid Data

Valid Data

Assumptions:

1. G < VIL (max) and Wn > VIH (min)

A(18:0)

Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access

En

DATA VALID

t

EFQZ

t

ETQX

t

ETQV

DQ(7:0)

Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access

A(18:0)

DQ(7:0)

G

t

GHQZ

Assumptions:

1. En < VIL (max) and Wn > VIH (min)

t

GLQV

t

GLQX

t

AVQV

DATA VALID

8

AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*

(-40°C to +125 °C) (VDD = 3.3V + 0.3)

Notes :
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.

1. Functional test performed with outputs disabled (G high).

2. Three-state is defined as 300mV change from steady-state output voltage.

SYMBOL PARAMETER MIN MAX UNIT

t

AVAV

1

Write cycle time 25 ns

t

ETWH

Device Enable to end of write 20 ns

t

AVET

Address setup time for write ( En - controlled) 0 ns

t

AVWL

Address setup time for write ( Wn - controlled) 0 ns

t

WLWH

Write pulse width 20 ns

t

WHAX

Address hold time for write (Wn - controlled) 2 ns

t

EFAX

Address hold time for Device Enable (En - controlled) 2 ns

t

WLQZ

2

Wn- controlled three-state time 10 ns

t

WHQX

2

Wn - controlled Output Enable time 5 ns

t

ETEF

Device Enable pulse width (En - controlled) 20 ns

t

DVWH

Data setup time 15 ns

t

WHDX

2

Data hold time 2 ns

t

WLEF

Device Enable controlled write pulse width 20 ns

t

DVEF

2

Data setup time 15 ns

t

EFDX

Data hold time 2 ns

t

AVWH

Address valid to end of write 20 ns

t

WHWL

1

Write disable time 5 ns

9

Assumptions:

1. G < VIL (max). If G > VIH (min) then Qn(8:0) will be
in three-state for the entire cycle.

2. G high for t

AVAV

cycle.

Wn

t

AVWL

Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access

A(18:0)

Q(7:0)

En

t

AVAV

2

D(7:0)

APPLIED DATA

t

DVWH

t

WHDX

t

ETWH

t

WLWH

t

WHAX

t

WHQX

t

WLQZ

t

AVWH

t

WHWL

t

EFDX

Assumptions & Notes:

1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle.

2. Either En scenario above can occur.

3. G high for t

AVAV

cycle.

A(18:0)

Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access

Wn

En

D(7:0)

APPLIED DATA

En

Q(7:0)

t

WLQZ

t

ETEF

t

WLEF

t

DVEF

t

AVAV

3

t

AVET

t

AVET

t

ETEF

t

EFAX

t

EFAX

or

10

DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)

(1 Second Data Retention Test)

Notes:

1. En = V

DD

- .2V, all other inputs = VDR or VSS.

2. Data retention current (I

DDR

) Tc = 25oC.

3. Not guaranteed or tested.

DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)

(10 Second Data Retention Test, TC=-40oC to +125oC)

Notes:

1. Performed at VDD (min) and VDD (max).

2. En = VSS, all other inputs = VDR or VSS.

3. Not guaranteed or tested.

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

V

DR

VDD for data retention 2.0 -- V

I

DDR

1,2

Data retention current (per byte) -- 4.0 mA

t

EFR

1,3

Chip select to data retention time 0 ns

t

R

1,3

Operation recovery time t

AVAV

ns

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

V

DD

1

VDD for data retention 3.0 3.6 V

t

EFR

2, 3

Chip select to data retention time 0 ns

t

R

2, 3

Operation recovery time t

AVAV

ns

V

DD

DATA RETENTION MODE

t

R

50%

50%

VDR > 2.0V

Figure 7. Low VDD Data Retention Waveform

t

EFR

En

11

12

PACKAGING

1. All exposed metalized areas must be plated per MIL-PRF-38535.

2. The lid is electrically connected to VSS.

3. Index mark configuration is optional.

4. Total weight is approx. 4.6 g.

Figure 9. 44-lead bottom brazed dual CFP (BBTFP) package

13

ORDERING INFORMATION
1024K8 SRAM:

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (g old).

3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed.

4. Extended Industrial Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -40°C to +125°C. Radiation neither

tested nor guaranteed.

Device Type:

- = 25ns access, 3.3V operation

Package Type:
(U) = 44-lead bottom brazed dual CFP (BBTFP)

Screening:
(P) = Prototype flow

(W) = Extended Industrial Temperature Range Flow (-40oC to +125oC)

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)

UT8Q1024K8 - * * * *

Aeroflex UTMC Core Part Number

14

1024K8 SRAM: SMD

5962 - 01532

* * *

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).

3. Total dose radiation must be specified when ordering.

Federal Stock Class Designator: No Options

Total Dose
(-) = None
(D) = 1E4 (10krad(Si))
(P) = 3E4 (30krad(Si)) (contact factory)
(L) = 5E4 (50krad(Si)) (contact factory)

Drawing Number: 01532

Device Type
01 = 25ns access time, 3.3V operation, Extended Industrial Temp (-40oC to +125oC)

Class Designator:
(T) = QML Class T
(Q) = QML Class Q

Case Outline:
(Y) = 44-lead dual cavity CFP

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)

**