Datasheet 5962R0153601VYC, 5962R0153601VYA, 5962R0153601QYX, 5962H0153601VYX, 5962H0153601VYC Datasheet (UTMC)

1

FEATURES

q 400.0 Mbps low jitter fully differential data path
q 200MHz clock channel
q 3.3 V power supply
q 10mA LVDS output drivers
q Cold sparing all pins
q Fast propagation delay of 3.5ns max
q Receiver input threshold < + 100 mV
q Radiation-hardened design; total dose irradiation testing to

MIL-STD-883 Method 1019

- Total-dose: 300 krad(Si) and 1 Mrad(Si)

- Latchup immune (LET > 100 MeV-cm2/mg)

q Packaging options:

- 48-lead flatpack

q Standard Microcircuit Drawing 5962-01536

- QML Q and V compliant part

q Compatible with ANSI/TIA/EIA 644-1995 LVDS

Standard

INTRODUCTION

The UT54LVDM328 is an Octal Bus Repeater utilizing Low
Voltage Differential Signaling (LVDS) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. LVDS I/O enable high speed data transmission
for point-to point or multi-drop interconnects. This device is
designed for use as a high speed differential repeater.

The UT54LVDM328 is a repeater designed specifically for the
bridging of multiple backplanes in a system. The
UT54LVDM328 utilizes low voltage differential signaling to
deliver high speed while consuming minimal power with
reduced EMI. The UT54LVDM328 repeats signals between
backplanes and accepts or drives signals onto the local bus.

The individual LVDS outputs can be put into Tri-State by use
of the enable pins.

All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.

OUT1+

END
IN1+

+

-

OUT2+

IN2+

+

-

IN1-

OUT1-

OUT2-

IN2-

Standard Products

UT54LVDM328 Octal 400 Mbps Bus LVDS Repeater

Data Sheet

August, 2002

Figure 1a. UT54LVDM328 Repeater Block Diagram

(Partial - see Page 2 for complete diagram)

2

OUT1+

END

IN1+

+

-

OUT2+

IN2+

+

-

IN1-

OUT1-

OUT2-

IN2-

OUT3+

IN3+

+

-

OUT4+

IN4+

+

-

IN3-

OUT3-

OUT4-

IN4-

OUT5+

IN5+

+

-

OUT6+

IN6+

+

-

IN5-

OUT5-

OUT6-

IN6-

OUT7+

IN7+

+

-

OUT8+

IN8+

+

-

IN7-

OUT7-

OUT8-

IN8-

Clk In+

Clk Out+

+

-

Clk In-

Clk Out-

ENCK

Figure 1b. UT54LVDM328 Repeater Diagram

3

PIN DESCRIPTION

Figure 2. UT54LVDM328 Pinout

UT54LVDM328

Bus Repeater

48
47

46

45
44

43

42
41

OUT3+

1IN1+

2

3
4

5
6
7

8IN3­9

10
11

12
13
14

15
16

IN3+

CLK In+

CLK In-

IN5-

17
18
19

20
21
22

23
24

IN6-

VSS

IN8+

IN8-

OUT1+

VDD

40

39
38

37
36
35

34
33

CLK OUT-

OUT5-

VDD

CLK OUT+

32

31
30

29

28
27
26

25

OUT8-

OUT6+

OUT7+

IN1-

IN2-

VDD

IN4+

IN4-

ENCK

END

IN5+

IN6+

VDD

IN7+

IN7-

OUT1­OUT2+
OUT2-

VSS

OUT3­OUT4+
OUT4-

VSS

OUT5+

VSS

OUT6-

VDD

OUT7­OUT8+

IN2+

VSS

Name # of Pins Description

INn+ 8 Non-inverting LVDS input

INn- 8 Inverting LVDS input

OUTn+ 8 Non-inverting LVDS output

OUTn- 8 Inverting LVDS Output

END 1 A logic low on the enable puts

the LVDS data output into Tri-

State and reduces the supply

current

ENCK 1 A logic low on the enable puts

the LVDS clock output into Tri-

State and reduces the supply

current

V

SS

5 Ground

V

DD

5 Power supply

CLK IN+ 1 Non-Inverting Clock LVDS

Input

CLK IN- 1 Inverting clock LVDS Input

CLK

OUT+

1 Non-Inverting Clock LVDS

Output

CLK

OUT-

1 Inverting Clock LVDS Output

4

APPLICATIONS INFORMATION

The UT54LVDM328 provides the basic bus repeater
function. The device operates as a 9 channel LVDS buffer.
Repeating the signal restores the LVDS amplitude, allowing
it to drive another media segment. This allows for isolation
of segments or long distance applications.

The intended application of these devices and signaling
technique is for both point-to-point baseband (single
termination) and multipoint (double termination) data
transmissions over controlled impedance media. The
transmission media may be printed-circuit board traces,
backplanes, or cables. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the
environment, and other application specific characteristics.)

Input Fail-Safe:

The UT54LVDM328 also supports OPEN, shorted and
terminated input fail-safe. Receiver output will be HIGH for
all fail-safe conditions.

PCB layout and Power System Bypass:

Circuit board layout and stack-up for the UT54LVDM328
should be designed to provide noise-free power to the device.
Good layout practice also will separate high frequency or high
level inputs and outputs to minimize unwanted stray noise
pickup, feedback and interference. Power system
performance may be greatly improved by using thin
dielectrics (4 to 10 mils) for power/ground sandwiches. This
increases the intrinsic capacitance of the PCB power system
which improves power supply filtering, especially at high
frequencies, and makes the value and placement of external
bypass capacitors less critical. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.01µF to

0.1µ F. Tantalum capacitors may be in the range of 2.2µF to
10µF. Voltage rating for tantalum capacitors should be at
least 5X the power supply voltage being used. It is
recommended practice to use two vias at each power pin of
the UT54LVDM328, as well as all RF bypass capacitor
terminals. Dual vias reduce the interconnect inductance and
extends the effective frequency range of the bypass
components.

The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and
isolation, as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the ground supply plane at frequent
intervals with vias. Frequent via placement also improves
signal integrity in signal transmission lines by providing short
paths for image currents which reduces signal distortion. The
planes should be pulled back from all transmission lines and
component mounting pads a distance equal to the width of
the widest transmission line from the internal power or
ground plane(s) whichever is greater. Doing so minimizes
effects on transmission line impedances and reduces
unwanted parasitic capacitances at component mounting
pads.

Compatibility with LVDS standard:

In backplane multidrop configurations, with closely spaced
loads, the effective differential impedance of the line is
reduced. If the mainline has been designed for 50 Ω
differential impedance, the loading effects may reduce this
to the 35Ω range depending upon spacing and capacitance
load. Terminating the line with a 35Ω load is a better match
than with 50Ω and reflections are reduced.

5

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175°C during burn-in and life test.

3. Test per MIL-STD-883, Method 1012.

4. For cold spare mode (VDD = VSS), V

I/O

may be -0.3V to the maximum recommended operating VDD +0.3V.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD

DC supply voltage -0.3 to 4.0V

V

I/O

Voltage on any pin -0.3 to (VDD + 0.3V)

T

STG

Storage temperature -65 to +150°C

P

D

Maximum power dissipation 800mW

T

J Maximum junction temperature

2

+150°C

Θ

JC

Thermal resistance, junction-to-case

3

22°C/W

I

I

DC input current

±10mA

SYMBOL PARAMETER LIMITS

V

DD

Positive supply voltage 3.3 to 3.6V

T

C

Case temperature range -55 to +125°C

V

IN

DC input voltage, receiver inputs 0 to 2.4V
DC input voltage, logic inputs 0 to VDD for END or ENCK

6

DC ELECTRICAL CHARACTERISTICS

1

(VDD = 3.3V + 0.3V; -55°C < TC < +125°C)

SYMBOL PARAMETER CONDITION MIN MAX UNIT

CMOS/TTL DC SPECIFICATIONS (EN)

V

IH

High-level input voltage 2.0 V

DD

V

V

IL

Low-level input voltage GND 0.8 V

I

IH

High-level input current VIN=3.6V; VDD = 3.6V -10 +10 µA

I

IL

Low-level input current VIN=0V; VDD = 3.6V -10 +10 µA

V

CL

Input clamp voltage ICL=-18mA -1.5 V

I

CS

Cold Spare Leakage current VIN=3.6V, VDD=V

SS

-20 +20 µΑ

LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)

V

OD

Differential Output Voltage RL= 35 Ω (See Figure 9) 250 450 mV

∆V

OD

Change in VOD between
complimentary output states

RL= 35 Ω (See Figure 9) 35 mV

V

OS

Offset Voltage 1.055 1.550 V

∆V

OS

Change in VOS between complimentary
output states

RL=35Ω 35 mV

I

OZ

Output Tri-State Current Tri-State output, VDD = 3.6V

V

OUT=VDD

or GND

+10 µΑ

I

CSOUT

Cold Sparing Leakage Current V

OUT

=3.6V, VDD=V

SS

-20 +20 µΑ

I

OS

2,3

Output Short Circuit Current V

OUT

+ OR V

OUT

= 0 V -25 mA

LVDS RECEIVER DC SPECIFICATIONS (IN+, IN-)

V

TH

3

Differential Input High Threshold VCM = +1.2V +100 mV

V

TL

3

Differential Input Low Threshold VCM = +1.2V -100 mV

V

CMR

Common Mode Voltage Range VID=210mV 0.2 2.00 V

I

IN

Input Current VIN = +2.4V, VDD = 3.6V -10 +10 µΑ

VIN = 0V, VDD = 3.6V -10 +10 µΑ

I

CSIN

Cold Sparing Leakage Current VIN=3.6V, VDD=V

SS

-20 +20 µΑ

RL= 35 Ω VOS=(VOH+VOL)

2

7

DC ELECTRICAL CHARACTERISTICS 1 (CON"T)

Notes:

1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.

2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed
maximum junction temperature specification.

3. Guaranteed by characterization.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

Supply Current

I

CCL

Total Supply Current RL = 35Ω

END, ENCK= V

DD, VDD

= 3.6V

220 ma

ICCZ Tri-State Supply Current END, ENCK = V

SS, VDD

= 3.6V 20 ma

8

AC SWITCHING CHARACTERISTICS

(VDD = +3.3V + 0.3V, TA = -55 °C to +125 °C)

Notes:

1. Guaranteed by design.

2. Guaranteed by characterization.

.

SYMBOL PARAMETER Conditions MIN MAX UNIT

t

PHZ

2

Disable Time (Active to Tri-State) High to Z
(See Figure 7)

RL= 35 Ω, CL = 10pf 4.5 ns

t

PLZ

2

Disable Time (Active to Tri-State) Low to Z
(See Figure 7)

RL= 35 Ω, CL = 10pf 4.5 ns

t

PZH

2

Enable Time (Tri-State to Active) Z to High
(See Figure 7)

RL= 35 Ω, CL = 10pf 11.0 ns

t

PZL

2

Enable Time (Tri-State to Active) Z to Low
(See Figure 7)

RL= 35 Ω, CL = 10pf 11.0 ns

t

LHT

1

Output Low-to-High Transition Time, 20% to 80%
(See Figures 4 and 5)

RL= 35 Ω, CL = 10pf 600 ps

t

HLT

1

Output High-to-Low Transition Time, 80% to 20%
(See Figures 4 and 5)

RL= 35 Ω, CL = 10pf 600 ps

t

PLHD

Propagation Low to High Delay
(See Figures 4 and 6)

RL= 35 Ω, CL = 10pf 3.5 ns

T

PHLD

Propagation High to Low Delay
(See Figures 4 and 6)

RL= 35 Ω, CL = 10pf 3.5 ns

T

SKEW

Differential Skew T

PHLD

- T

PLHD

(See Figures 4 and 6)

900 ps

T

CCS

Output Channel-to-Channel Skew
(See Figures 4 and 6)

500 ps

9

R

R

IN+

Pulse

Generator

50Ω

Figure 4. LVDS Output Load

R

IN-

50Ω C

L

D

C

L

R

L

t

HLT

20%

80%

0V

20%

80%

t

LHT

Figure 5. LVDS Output Transition Time

V

DIFF

t

PLHD

t

PHLD

Vdiff = 0V

Vdiff = 0V

IN

OUT

Figure 6. Propagation Delay Low-to-High and High-to-Low

10

EN

t

PLZ

t

PZL

50%

50%

V

OL

0VDiff

0VDiff

V

OH

V

DD

V

DD/2

V

DD/2

50%

t

PZH

t

PHZ

Figure 7. Output active to TRI-STATE and TRI-STATE to active

50%

OUT

OUT

TCCS

Vdiff = 0V

Vdiff = 0V

OUT 0

OUT 1

Figure 8. Output Channel-to-Channel Skew

Figure 9. Driver VOD and VOS Test Circuit or Equivalent Circuit

D

D

IN

D

OUT-

D

OUT+

20pF

Driver Enabled

Generator

50Ω

RL = 35Ω

V

OD

20pF

11

PACKAGING

Notes:

1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.

2. The lid is electrically connected to VSS.

3. Lead finishes are in accordance to MIL-PRF-38535.

4. Package dimensions and symbols are similar to MIL-STD-1835 Requirement 101, Configuration B.

5. Lead position and coplanarity are not measured.

6. ID mark symbol is vendor option.

7. With solder, increase maximum by 0.003.

Figure 10. 48-pin Flatpack

12

ORDERING INFORMATION

UT54LVDM328 Bus LVDS Repeater:

UT 54LVDM328 - * * * * *

Device Type:
UT54 LVDM328 Bus LVDS Repeater

Access Time:
Not applicable

Package Type:
(U) = 48-lead Flatpack (dual-in-line)

Screening:
(C) = Military Temperature Range flow
(P) = Prototype flow

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither

tested nor guaranteed.

4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.

Radiation neither tested nor guaranteed.

13

UT54LVDM328 Bus LVDS Repeater: SMD

5962 -

* * *

Federal Stock Class Designator: No Options

Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)

Drawing Number: 01536

Device Type
01 = Bus LVDS Repeater

Class Designator:
(Q) = QML Class Q
(V) = QML Class V

Case Outline:
(Y) = 48-lead Flatpack (dual-in-line)

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)

**

01536

Notes:

1.Lead finish (A,C, or X) must be specified.

2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.

14

NOTES