Datasheet 5962R9687301QYC, 5962R9687301QXX, 5962R9687301QXC, 5962R9687301QXA, 5962R9687302QYA Datasheet (UTMC)

1

Standard Products

UT28F64 Radiation-Hardened 8K x 8 PROM

Data Sheet

August 2001

FEATURES

q Programmable, read-only, asynchronous, radiation-

hardened, 8K x 8 memory

- Supported by industry standard programmer

q 35ns and 45ns maximum address access time (-55 oC to

+125 oC)

q TTL compatible input and TTL/CMOS compatible output

levels

q Three-state data bus
q Low operating and standby current

- Operating: 100mA maximum @28.6MHz

• Derating: 3mA/MHz

- Standby: 500µA maximum (post-rad)

q Radiation-hardened process and design; total dose

irradiation testing to MIL-STD-883, Method 1019

- Total dose: 1E6 rad(Si)

- LETTH(0.25) ~ 100 MeV-cm2/mg

- SEL Immune >128 MeV-cm2/mg

- Saturated Cross Section cm2 per bit, 1.0E-11

- 1.2E-8 errors/device-day, Adams 90% geosynchronous
heavy ion

- Memory cell LET threshold: >128 MeV-cm2/mg

q QML Q & V compliant part

- AC and DC testing at factory

q Packaging options:

- 28-pin 100-mil center DIP (0.600 x 1.4)

- 28-lead 50-mil center flatpack (0.490 x 0.74)

q VDD: 5.0 volts + 10%
q Standard Microcircuit Drawing 5962-96873

PRODUCT DESCRIPTION

The UT28F64 amorphous silicon anti-fuse PROM is a high
performance, asynchronous, radiation-hardened,
8K x 8 programmable memory device. The UT28F64 PROM
features fully asychronous operation requiring no external clocks
or timing strobes. An advanced radiation-hardened twin-well
CMOS process technology is used to implement the UT28F64.
The combination of radiation- hardness, fast access time, and low
power consumption make the UT28F64 ideal for high speed
systems designed for operation in radiation environments.

DECODER

MEMORY

ARRAY

SENSE AMPLIFIER

PROGRAMMING

CONTROL

LOGIC

DQ(7:0)

A(12:0)

CE

PE

OE

Figure 1. PROM Block Diagram

2

DEVICE OPERATION

The UT28F64 has three control inputs: Chip Enable (CE),
Program Enable (PE), and Output Enable (OE); thirteen address
inputs, A(12:0); and eight bidirectional data lines, DQ(7:0). CE
is the device enable input that controls chip selection, active, and
standby modes. Asserting CE causes IDD to rise to its active value

and decodes the thirteen address inputs to select one of 8,192
words in the memory. PE controls program and read operations.
During a read cycle, OE must be asserted to enable the outputs.

PIN NAMES

Table 1. Device Operation Truth Table

1

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the

device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

2. Test per MIL-STD-883, Method 1012, infinite heat sink.

NC

A12

A7
A6

A5
A4
A3
A2
A1

A0

DQ0
DQ1

DQ2

V

SS

V

DD

PE
NC
A8
A9

A11
OE
A10
CE
DQ7
DQ6

DQ5
DQ4

DQ3

PIN CONFIGURATION

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A(12:0) Address

CE Chip Enable
OE Output Enable

PE Program Enable

DQ(7:0) Data Input/Data Output

OE PE CE I/O MODE MODE

X 1 1 Three-state Standby

0 1 0 Data Out Read
1 0 0 Data In Program
1 1 0 Three-state

Read

2

SYMBOL PARAMETER LIMITS UNITS

V

DD

DC supply voltage -0.3 to 7.0 V

V

I/O

Voltage on any pin -0.5 to (V

DD

+ 0.5) V

T

STG

Storage temperature -65 to +150 °C

P

D

Maximum power dissipation 1.5 W

T

J

Maximum junction temperature +175 °C

Θ

JC Thermal resistance, junction-to-case

2

3.3 °C/W

I

I

DC input current

±10

mA

3

RECOMMENDED OPERATING CONDITIONS

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(V

DD

= 5.0V ±10%; -55 °C < TC < +125 °C)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).

1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

4. Functional test.

5. Derates at 2.5mA/MHz.

SYMBOL PARAMETER LIMITS UNITS

V

DD

Positive supply voltage 4.5 to 5.5 V

T

C

Case temperature range -55 to +125 °C

V

IN

DC input voltage 0 to V

DD

V

SYMBOL PARAMETER CONDITION MINIMUM MAXIMUM UNIT

V

IH

High-level input voltage (TTL) 2.4 V

V

IL

Low-level input voltage (TTL) 0.8 V

V

OL1

Low-level output voltage IOL = 4.8mA, V

DD

= 4.5V (TTL) 0.4 V

V

OL2

Low-level output voltage IOL = 200µA, VDD = 4.5V (CMOS) V

SS

+ 0.05 V

V

OH1

High-level output voltage IOH = -400µA, VDD = 4.5V (TTL)

I

OH

= -2.0mA

2.4

3.5

V

V

OH2

High-level output voltage IOH = -200µA VDD = 4.5V (CMOS)

IOH = -100µA

4.45

VDD - 0.3

V

C

IN

1

Input capacitance ƒ = 1MHz, VDD = 5.0V 15 pF

C

IO

1, 4

Bidirectional I/O capacitance ƒ = 1MHz, VDD = 5.0V

V

OUT

= 0V

15 pF

I

IN

Input leakage current VIN = 0V to V

DD

-1 1 µA

I

OZ

Three-state output leakage
current

VO = 0V to VDD
VDD = 5.5V
OE = 5.5V

-10 10 µA

I

OS

2,3

Short-circuit output current VDD = 5.5V, VO = V

DD

VDD = 5.5V, VO = 0V

-90

90 mA

mA

IDD(OP)

5

Supply current operating
@28.6MHz (35ns product)

@22.2MHz (45ns product)

TTL input levels (I

OUT

= 0),
VIL = 0.2V
VDD, PE = 5.5V

100

85

mA

IDD(SB)

post-rad

Supply current standby CMOS input levels ,

VIL = VSS to 0.25V
CE = V

DD

-025, V

IH

= VDD -0.25V

500 µA

4

READ CYCLE

A combination of PE greater than VIH(min), and CE less than
VIL(max) defines a read cycle. Read access time is measured
from the latter of device enable, output enable, or valid address

to valid data output.
An address access read is initiated by a change in address inputs

while the chip is enabled with OE asserted and PE deasserted.
Valid data appears on data output, DQ(7:0), after the specified
t

AVQV

is satisfied. Outputs remain active throughout the entire

cycle. As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum read
cycle time.

The chip enable-controlled access is initiated by CE going active
while OE remains asserted, PE remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
t

ELQV

is satisfied, the eight-bit word addressed by A(12:0)

appears at the data outputs DQ(7:0).
Output enable-controlled access is initiated by OE going active

while CE is asserted, PE is deasserted, and the addresses are
stable. Read access time is t

GLQV

unless t

AVQV

or t

ELQV

have

not been satisfied.

AC CHARACTERISTICS READ CYCLE (Post-Radiation)*

(V

DD

= 5.0V ±10%; -55 °C < TC < +125 °C)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).

1. Functional test.

2. Three-state is defined as a 400mV change from steady-state output voltage.

SYMBOL PARAMETER 28F64-35

MIN MAX

28F64-45

MIN MAX

UNIT

t

AVAV

1

Read cycle time 35 45 ns

t

AVQV

Read access time 35 45 ns

t

AXQX

2

Output hold time 0 0 ns

t

GLQX

2

OE-controlled output enable time 0 0 ns

t

GLQV

OE-controlled access time 15 15 ns

t

GHQZ

OE-controlled output three-state time 15 15 ns

t

ELQX2

CE-controlled output enable time 0 0 ns

t

ELQV

CE-controlled access time 35 45 ns

t

EHQZ

CE-controlled output three-state time 15 15 ns

5

RADIATION HARDNESS

The UT28F64 PROM incorporates special design and layout
features which allow operation in high-level radiation
environments. UTMC has developed special low-temperature
processing techniques designed to enhance the total-dose
radiation hardness of both the gate oxide and the field oxide while

maintaining the circuit density and reliability. For transient
radiation hardness and latchup immunity, UTMC builds all
radiation-hardened products on epitaxial wafers using an
advanced twin-tub CMOS process. In addition, UTMC pays
special attention to power and ground distribution during the
design phase, minimizing dose-rate upset caused by rail collapse.

RADIATION HARDNESS DESIGN SPECIFICATIONS

1

Note:

1. The PROM will not latchup during radiation exposure under recommended operating conditions.

Figure 2. PROM Read Cycle

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

AVQV

t

AXQX

t

EHQZ

t

GHQZ

A(12:0)

CE

OE

DQ(7:0)

t

GLQX

t

ELQX

Total Dose 5.0E5 rad(Si)
Latchup LET Threshold >128

MeV-cm2/mg

Memory Cell LET Threshold >128

MeV-cm2/mg

Transient Upset LET Threshold 54

MeV-cm2/mg

Transient Upset Device Cross Section @ LET=128 MeV-cm2/mg

1E-6

cm

2

6

Notes:

1. 50pF including scope probe and test socket.

2. Measurement of data output occurs at the low to high or high to low transition mid-point
(TTL input = 1.5V).

90%

Figure 3. AC Test Loads and Input Waveforms

Input
Pulses

10%

< 5ns < 5ns

TTL

0V

3.0V

330 ohms

V

REF

=1.73V

50pF

90%

10%

7

Figure 4. 28-Pin 100-mil Center DIP (0.600 x 1.4)

Notes:

1. Seal ring to be electrically isolated.

2. All exposed metalized areas to be plated per MIL-PRF-38535.

3. Ceramic to be opaque.

4. Dimension letters refer to MIL-STD-1835.

D

1.400 ± 0.020

PIN NO. 1 ID.

S1

0.005 MIN.

S2

0.005 MIN.

E

0.595 ± 0.015

E1

0.600

C

0.010

A

0.175 MAX.

L

0.200

0.125

e

0.100

b

0.018 ±.002

Q

0.060

0.015

TOP VIEW END VIEW

b

0.065

0.045

SIDE VIEW

8

Notes:

1. All exposed metalized areas are gold plated over electroplated nickel
per MIL-PRF-38535.

2. The lid is electrically connected to VSS.

3. Lead finishes are in accordance with MIL-PRF-38535.

4. Dimension letters refer to MIL-STD-1835.

5. Lead position and coplanarity are not measured.

6. ID mark symbol is vendor option.

7. With solder, increase maximum by 0.003.

Figure 5. 28-Lead 50-mil Center Flatpack (0.490 x 0.74)

0.015

0.008

0.015

0.008

PIN NO. 1 ID.

6

26 PLACES

0.050 BSC
e

D

0.740 MAX

E1

0.550 MAX

5

-B-

7

S1
(4) PLACES

0.000 MIN.

7

-D-

-C-

A

0.115

0.045

0.045

0.026

L

0.370

0.250

E2

0.180 MIN

E3

0.030 MIN

E

0.520

0.460

-H-

c

0.009

0.004

0.040

0.022

0.015

28 PLACES

-A-

H A-B

D5SS

0.010

M

H

A-B

D

5

S

SM

0.036

TOP VIEW

END VIEW

b

k

k

Q

9

ORDERING INFORMATION

64K PROM: SMD

Lead Finish:
(A) = Solder
(C) = Gold

(X) = Optional

Case Outline:
(X) = 28-pin DIP
(Y) = 28-lead Flatpack

Class Designator:
(Q) = Class Q
(V) = Class V

Device Type
(01) = 35ns Access Time, TTL inputs, CMOS/TTL compatible outputs
(02) = 45ns Access Time, TTL inputs, CMOS/TTL compatible outputs

Drawing Number: 96873

Total Dose:
(G) = 5E5 rads(Si)
(F) = 3E5 rads(Si)
(R) = 1E5 rads(Si)

Federal Stock Class Designator: No options

5962 * 96873 * * * *

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.

4. Lead finish: Factory programming either solder or gold. Field programming gold only.

10

64K PROM

UT **** *** - * * * * * *

Total Dose:
( ) = None

Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional

Screening:
(C) = Mil Temp
(P) = Prototype

Package Type:
(P) = 28-lead DIP
(U) = 28-lead Flatpack

Access Time:
(35) = 35ns access time, TTL compatible inputs, CMOS/TTL compatible outputs
(45) = 45ns access time, TTL compatible inputs, CMOS/TTL compatible outputs

Device Type Modifier:
(T) = TTL compatible inputs and CMOS/TTL compatible outputs

Device Type:
(28F64) = 8Kx8 One Time Programmable PROM

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may
not be specified.

4. Prototype flow per UTMC Manufacturing Flows Document. Devices have prototype assembly and are tested at 25°C only. Radiation characteristics
are neither tested nor guaranteed and may not be specified. Lead finish is gold only.

5. Lead finish: Factory programming either solder or gold. Field programming gold only.