Datasheet 5962R9563801VYX, 5962R9563801VYC, 5962R9563801VYA, 5962R9563801VQX, 5962R9563801VQA Datasheet (UTMC)

Standard Products

UT69RH051 Radiation-Hardened MicroController

Data Sheet

May 2003

FEATURES

q Three 16-bit timer/counters

- High speed output

- Compare/capture

- Pulse width modulator

- Watchdog timer capabilities

q 256 bytes of on-chip data RAM
q 32 programmable I/O lines
q 7 interrupt sources
q Programmable serial channel with:

- Framing error detection

- Automatic address recognition

q TTL and CMOS compatible logic levels
q 64K external data and program memory space
q MCS-51 fully compatible instruction set

q Flexible clock operation

- 1Hz to 20MHz with external clock

- 2MHz to 20MHz using internal oscillator with external
crystal

q Radiation-hardened process and design; total dose irradia-

tion testing MIL-STD-883 Method 1019

- Total dose: 1.0E6 rads(Si)

- Latchup immune

q Packaging options:

- 40-pin 100-mil center DIP (0.600 x 2.00)

- 44-lead 25-mil center Flatpack (0.670 x 0.800)

q Standard Microcircuit Drawing 5962-95638 available

- QML Q & V compliant

PSEN
ALE

EA

RST

XTAL1

B

REGISTER

MICRO-

S EQUENCER

OSC.

XTAL2

PORT 0

DRIVERS

REG ISTER

RAM ADDRESS

ACC

TMP2

REGISTER

INSTRUCTION

RAM

ALU

PSW TMP3

PORT 1

LATCH

PORT 1

DRIVERS

P1.0 - P1.7

PORT 0

LATCH

TMP1 SPECIAL FUNCTION

PORT 2

LATCH

STACK

POINTER

REGISTERS,

TIMERS,

PCA,

SERIAL PORT

Figure 1. UT69RH051 MicroController Block Diagram

PORT 2

DRIVERS

PROGRAM

ADDRESS

REGISTER

BUFFER

PC

INCREMENTER

PROGRAM

COUNTER

DPTR

PORT 3

LATCH

PORT 3

DRIVERS

P3.0 - P3.7

1.0 INTRODUCTION

Table 1. Port 1 Alternate Functions

The UT69RH051 is a radiation-tolerant 8-bit microcontroller
that is pin equivalent to the MCS-51 industry standard
microcontroller when in a 40-pin DIP. The UT69RH051’s static
design allows operation from 1Hz to 20MHz. This data sheet
describes hardware and software interfaces to the UT69RH051.

2.0 SIGNAL DESCRIPTION
VDD: +5V Supply voltage

VSS: Circuit Ground

Port 0 (P0.0 - P0.7): Port 0 is an 8-bit port. Port 0 pins are used

as the low-order multiplexed address and data bus during
accesses to external program and data memory. Port 0 pins use
internal pullups when emitting 1’s and are TTL compatible.

Port 1 (P1.0 - P1.7): Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The output buffers can drive TTL loads. When
the Port 1 pins have 1’s written to them, they are pulled high by
the internal pullups and can be used as inputs in this state. As
inputs, any pins that are externally pulled low sources current
because of the pullups. In addition, Port 1 pins have the alternate
uses shown in table 1.

Port 2 (P2.0 - P2.7): Port 2 is an 8-bit port. Port 2 pins are used
as the high-order address bus during accesses to external Program
Memory and during accesses to external Data Memory that uses
16-bit addresses (i.e., MOVX@DPTR). Port 2 uses internal
pullups when emitting 1’s in this mode. During operations that
do not require a 16-bit address, Port 2 emits the contents of the
P2 Special Function Registers (SFR). The pins have internal
pullups and drives TTL loads.

Port 3 (P3.0 - P3.7): Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The output buffers can drive TTL loads. When
the Port 3 pins have 1’s written to them, they are pulled high by
the internal pullups and can be used as inputs in this state. As
inputs, any pins that are externally pulled low sources current
because of the pullups. In addition, Port 3 pins have the alternate
uses shown in table 2.

Port

Pin

P1.0 T2 External clock input to Timer/

P1.1 T2EX Timer/Counter 2 Capture/Reload

P1.2 ECI External count input to PCA
P1.3 CEX0 External I/O for PCA capture/

P1.4 CEX1 External I/O for PCA capture/

P1.5 CEX2 External I/O for PCA capture/

P1.6 CEX3 External I/O for PCA capture/

P1.7 CEX4 External I/O for PCA capture/

Port

Pin

P3.0 RXD Serial port input
P3.1 TXD Serial port output
P3.2 INT0 External interrupt 0
P3.3 INT1 External interrupt 1
P3.4 T0 External clock input for Timer 0
P3.5 T1 External clock input for Timer 1
P3.6 WR External Data Memory write

Alternate

Name

Table 2. Port 3 Alternate Functions

Alternate

Name

Alternate Function

Counter 2

trigger and direction control

compare Module 0

compare Module 1

compare Module 2

compare Module 3

compare Module 4

Alternate Function

strobe

P3.7 RD External Data Memory read strobe

2

RST: Reset Input. A high on this input for 24 oscillator periods
while the oscillator is running resets the device. All ports and
SFRs reset to their default conditions. Internal data memory is
undefined after reset. Program execution begins within 12
oscillator periods (one machine cycle) after the RST signal is
brought low. RST contains an internal pulldown resistor to allow
implementing power-up reset with only an external capacitor.

ALE: Address Latch Enable. The ALE output is a pulse for
latching the low byte of the address during accesses to external
memory. In normal operation, the ALE pulse is output every sixth
oscillator cycle and may be used for external timing or clocking.
However, during each access to external Data Memory (MOVX
instruction), one ALE pulse is skipped.

2.1 Hardware/Software Interface

2.1.1 Memory

The UT69RH051 has a separate address space for Program and
Data Memory. Internally, the UT69RH051 contains 256 bytes
of Data Memory. It addresses up to 64Kbytes of external Data
Memory and 64Kbytes of external Program Memory.

2.1.1.1 Program Memory

There is no internal program memory in the UT69RH051. All
program memory is accessed as external through ports P0 and
P2. The EA pin must be tied to VSS (ground) to enable access to

external locations 0000H through 7FFFH. Following reset, the
UT69RH051 fetches the first instruction at address 0000h.

PSEN: Program Store Enable. This active low signal is the read
strobe to the external program memory. PSEN activates every
sixth oscillator cycle except that two PSEN activations are
skipped during external data memory accesses.

EA: External Access Enable. This pin should be strapped to VSS
(Ground) for the UT69RH051.

XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.

2.1.1.2 Data Memory

The UT69RH051 implements 256 bytes of internal data RAM.
The upper 128 bytes of this RAM occupy a parallel address space
to the SFRs. The CPU determines if the internal access to an
address above 7FH is to the upper 128 bytes of RAM or to the

SFR space by the addressing mode of the instruction. If direct
addressing is used, the access is to the SFR space. If indirect
addressing is used, the access is to the internal RAM. Stack
operations are indirectly addressed so the upper portion of RAM
can be used as stack space. Figure 3 shows the organization of
the internal Data Memory.

The first 32 bytes are reserved for four register banks of eight
bytes each. The processor uses one of the four banks as its
working registers depending on the RS1 and RS0 bits in the PSW
SFR. At reset, bank 0 is selected. If four register banks are not
required, use the unused banks as general purpose scratch pad
memory. The next 16 bytes (128 bits) are individually bit
addressable. The remaining bytes are byte addressable and can
be used as general purpose scratch pad memory. For addresses
0 - 7FH, use either direct or indirect addressing. For addresses

larger than 7FH, use only indirect addressing.
In addition to the internal Data Memory, the processor can access

64Kbytes of external Data Memory. The MOVX instruction
accesses external Data Memory.

2.1.2 Special Function Registers

Table 3 contains the SFR memory map. Unoccupied addresses
are not implemented on the device. Read accesses to these
addresses will return unknown values and write accesses will
have no effect.

3

(T2) P1.0
(T2EX) P1.1
(ECI) P1.2
(CEX0) P1.3
(CEX1) P1.4
(CEX2) P1.5
(CEX3) P1.6
(CEX4) P1.7

RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7

XTAL2
XTAL1

V

SS

1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

V

DD

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)

Figure 2a. UT69RH051 40-Pin DIP Connections

V

(T2) P1.0

SS

(T2EX) P1.1

NC
(ECI) P1.2
(CEX0) P1.3
(CEX1) P1.4
(CEX2) P1.5
(CEX3) P1.6
(CEX4) P1.7
RST
(RXD) P3.0
(TXD) P3.1

(INTO ) P3.2
(INT1) P3.3
(TO) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7

XTAL2
XTAL1

V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

V

DD

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)

P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
NC

V

DD

Figure 2b. UT69RH051 44-Pin Flatpack Connections

4

8 BYTES

INDIRECT

ACCESS

ONLY

DIRECT OR

INDIRECT

ACCESS

F8

F0

88
80
78
70

38
30

28
20
18

10
08
00

FF

F7

•

•

•

•

•

•

•

•

•

8F
87
7F
77

•

•

•

3F
37

2F

ADDRESSABLE

27
1F
17
0F
07

SCRATCH

PAD AREA

BIT

SEGMENT

REGISTER

BANKS

Figure 3. Internal Data Memory Organization

2.1.3 Reset

The reset input is the RST pin. To reset, hold the RST pin high
for a minimum of 24 oscillator periods while the oscillator is
running. The CPU generates an internal reset from the external
signal. The port pins are driven to the reset state as soon as a valid
high is detected on the RST pin.

While RST is high, PSEN and the port pins are pulled high; ALE
is pulled low. All SFRs are reset to their reset values as shown
in table 3. The internal Data Memory content is indeterminate.

The processor will begin operation one machine cycle after the
RST line is brought low. A memory access occurs immediately
after the RST line is brought low, but the data is not brought into
the processor. The memory access repeats on the next machine
cycle and actual processing begins at that time.

5

Table 3. SFR Memory Registers

F8 CH

00000000

F0 B

CCAP0H

XXXXXXXX

CCAP1H

XXXXXXXX

CCAP2H

XXXXXXXX

CCAP3H

XXXXXXXX

CCAP4H

XXXXXXXX

FF

F7

00000000

E8 CL

00000000

E0 ACC

CCAP0L

XXXXXXXX

CCAP1L

XXXXXXXX

CCAP2L

XXXXXXXX

CCAP3L

XXXXXXXX

CCAP4L

XXXXXXXX

EF

E7

00000000

D8 CCON

00X00000

D0 PSW

CMOD

OOXXX000

CCAPM0

X00000000

CCAPM1

X00000000

CCAPM2

X00000000

CCAPM3

X00000000

CCAPM4

X00000000

DF

D7

00000000

C8 T2CON

00000000

T2MOD

XXXXXX00

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

TH2

00000000

CF

C0 C7

B8 IP

X0000000

B0 P3

11111111

A8 IE

00000000

SADEN

00000000

SADDR

00000000

IPH

X00000000

BF

B7

AF

A0 P2

11111111

98 SCON

00000000

SBUF

XXXXXXXX

90 P1

11111111

88 TCON

00000000

80 P0

11111111

Notes:

1. Values shown are the reset values of the registers.

2. X = undefined.

TMOD

00000000

SP

00000111

TL0

00000000

DPL

00000000

TL1

00000000

DPH

00000000

TH0

00000000

TH1

00000000

PCON

00XX00XX

A7

9F

97

8F

87

6

3.0 RADIATION HARDNESS

The UT69RH051 incorporates special design and layout features
which allow operation in high-level radiation environments.
UTMC has developed special low-temperature processing
techniques designed to enhance the total-dose radiation hardness
of both the gate oxide and the field oxide while maintaining the

circuit density and reliability. For transient radiation hardness
and latchup immunity, UTMC builds all radiation-hardened
products on epitaxial wafers using an advanced twin-tub CMOS
process. In addition, UTMC pays special attention to power and
ground distribution during the design phase, minimizing dose­rate upset caused by rail collapse.

RADIATION HARDNESS DESIGN SPECIFICATIONS

1

Total Dose 1.0E6 rad(Si)
LET Threshold 20

Neutron Fluence 1.0E14

Saturated Cross-Section (1Kx8) 1E-4

Single Event Upset 1.3E-7

Single Event Latchup

Note:

1. Worst case temperature T

2. Adams 90% worst case environment (geosynchronous).

1

= +125 °C.

A

4.0 ABSOLUTE MAXIMUM RATINGS

1

LET>128

MeV-cm2/mg

n/cm

cm2/device

errors/device-day

MeV-cm2/mg

(Referenced to VSS)

SYMBOL PARAMETER LIMITS UNITS

V

DD

V

I/O

DC Supply Voltage -0.5 to 7.0 V
Voltage on Any Pin -0.5 to VDD+0.3V V

2

2

T

STG

P

D

T

J

Θ

JC

I

I

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2. Test per MIL-STD-883, Method 1012.

Storage Temperature -65 to +150 °C

Maximum Power Dissipation 750 mW
Maximum Junction Temperature 175 °C

Thermal Resistance, Junction-to-Case
DC Input Current

2

10 °C/W

±10

mA

7

5.0 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

V

= 5.0V ±10%; TA = -55°C < TC < +125°C)

DD

SYMBOL PARAMETER CONDITION MINIMUM MAXIMUM UNIT

V
V

Low-level Input Voltage 0.8 V

IL

High-level Input Voltage

IH

2.0 V

(except XTAL, RST)

V

IH1

High-level Input Voltage

3.85 V

(XTAL)

V

OL

Low-level Output Voltage

1

IOL = 100µA 0.3 V

(Ports 1, 2 and 3)

IOL = 1.6mA 0.45 V
IOL = 3.5mA 1.0 V

V

OL1 Low-level Output Voltage

1,2

IOL = 200µA 0.3 V

(Port 0, ALE, PSEN, PROG)

IOL = 3.2mA 0.45 V
IOL = 7.0mA 1.0 V

V

OH High-level Output Voltage

3

IOH = -10µA 4.2 V

(Ports 1, 2, and 3
ALE and PSEN)

IOH = -30µA 3.8 V
IOH = -60µA 3.0 V

V

OH1

High-level Output Voltage

IOH = -200µA 4.2 V

(Port 0 in External Bus Mode)

IOH = -3.2mA 3.8 V
IOH = -7.0mA 3.0 V

I

IL

I

IL

I

LI

I

LI

C

IO

I

DD

Logical 0 Input Current
(Ports 1, 2, and 3)

Logical 0 Input Current
(XTAL 1)

Input Leakage Current
(Port 0)

Input Leakage Current
(XTAL1)

4

Pin Capacitance @ 1MHZ, 25°C 15 pF
Power Supply Current: @16MHz

VIN = 0.0V
VCC = 5.5V
VIN = 0.0V
VCC = 5.5V
VIN = 0.0V or V
V

= 5.5V

CC

VIN = 0.0V or V
V

= 5.5V

CC

@20 MHz

CC

CC

-50

-65

-65 µA

±25
±65

±65 µA

95

120

µA

µA

mA

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883.

1. Under steady state (non-transient) conditions, IOL must be limited externally as follows:
Maximum IOL per port pin: 10mA
Maximum IOL per 8-bit port- Port 0: 26mA

Maximum total IOL for all output pins: 71mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and ports 1 and 3. The noise is due to external bus
capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operations. In applications where capacitance loading

exceeds 100 pF, the noise pulse on the ALE may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a schmitt trigger or use an address latch
with a schmitt trigger strobe input.

3. Capacitive loading ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VDD-0.3 specification when the address lines are stabilizing.

4. Capacitance measured for initial qualification or design changes which may affect the value.

Ports 1, 2, & 3: 15mA

8

V

DD

I

V

V

DD

DD

DD

V

DD

RST

P0

EA

(NC)

CLOCK
SIGNAL

XTAL2
XTAL1

V

SS

GND

t

= t

CLCH

= 5ns

CHCL

Figure 4. I

Test Condition, Active Mode

DD

All other pins

disconnected

V

-0.5

DD

0.45V

0.7 V

0.2 V

DD

DD

-0.1
t

CHCL

t

CHCX

t

CLCL

t

CLCH

t

CHCX

Figure 5. Clock Signal Waveform for IDD Tests in Active and Idle Modes

t

CLCH

= t

CHCL

= 5ns

9

6.0 AC CHARACTERISTICS READ CYCLE (Post-Radiation)*

(V

= 5.0V ±10%; -55 °C < TC < +125 °C)

DD

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

t

CLCL

1/t

CLCL

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

AVIV

t

PLAZ

t

RLRH

t

WLWH

t

RLDV

Clock Period 50 ns
Oscillator Frequency 20 MHz
ALE Pulse Width 2 t
Address Valid to ALE Low t

1

Address Hold after ALE Low t

ALE Low to Valid Instruction 4 t
ALE Low to PSEN Low t
PSEN Pulse Width 3 t
PSEN Low to Valid Instruction In 3 t

1

1

Input Instruction Hold after PSEN 0 ns

Input Instruction Float after PSEN t

Address to Valid Instruction In 5 t

1

PSEN Low to Address Float 10 ns

RD Pulse Width 6 t
WR Pulse Width 6 t
RD Low to Valid Data In 5 t

-40 ns

CLCL

-40 ns

CLCL

-30 ns

CLCL

-100 ns

CLCL

-30 ns

CLCL

-45 ns

CLCL

-105 ns

CLCL

-25 ns

CLCL

-105 ns

CLCL

-100 ns

CLCL

-100 ns

CLCL

-165 ns

CLCL

t

RHDX1

1

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

QVWX

t

WHQX

t

QVWH

1

t

RLAZ

t

WHLH

Note:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).

1. Guaranteed, but not tested.

Data Hold After RD High 0 ns

Data Float After RD High 2 t

ALE Low Valid Data In 8 t
Address to Valid Data In 9 t
ALE Low to RD or WR Low 3 t
Address Valid to WR Low 4 t
Data Valid Before WR High t
Data Hold After WR High t
Data Valid to WR High 7 t

RD Low to Address Float 0 ns

RD or WR High to ALE High t

-60 ns

CLCL

-150 ns

CLCL

-165 ns

CLCL

-50 3 t

CLCL

-130 ns

CLCL

-33 ns

CLCL

-33 ns

CLCL

-150 ns

CLCL

-40 t

CLCL

+50 ns

CLCL

+40 ns

CLCL

10

t

LHLL

ALE

PSEN

RD

PORT 0

ALE

PSEN

PORT 0

PORT 2

t

t

AVLL

t

A0 - A7

LLPL

LLAX

t

AVIV

t

LLIV

t

PLPH

t

PLIV

t

t

PLAZ

t

PXIX

A8 - A15 A8 - A15

PXIZ

A0 - A7INSTR IN

Figure 6. External Program Memory Read Timing Waveforms

t

LHLL

t

LLDV

t

LLWL

t

LLAX

t

RLDV

t

AVLL

A0 -A7 FROM RI OR DPL INSTR IN

t

RLAZ

t

RLRH

t

RHDX

DATA IN A0 - A7 FROM PCL

t

WHLH

t

RHDZ

PORT 2

ALE

PSEN

WR

PORT 0

PORT 2

t

AVWL

t

AVDV

P2.0 - P2.7 OR A8 -A15 FROM DPH

Figure 7. External Data Memory Read Cycle Waveforms

t

LHLL

t

AVLL

A0 -A7 FROM RI OR DPL

t

LLAX

t

AVWL

P2.0 - P2.7 OR A8 -A15 FROM DPH A8 - A15 FROM PCH

t

LLWL

t

QVWX

t

WLWH

t

QVWH

DATA OUT A0 - A7 FROM PCL

Figure 8. External Data Memory Write Cycle Waveforms

A8 - A15 FROM PCH

t

WHLH

t

WHQX

INSTR IN

11

7.0 SERIAL PORT TIMING CHARACTERISTICS

(VDD = 5.0V ±10%; -55°C < TC < +125°C)

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

1

t

XLXL

t

QVXH

t

XHQX

1

t

XHDX

t

XHDV

Note:

1. Guaranteed, but not tested.

ALE

CLOCK

OUTPUT DATA

(WRITE TO SBUF)

INPUT DATA

(CLEAR RI)

Serial Port Clock Period 12 t

Output Data Setup to Clock Rising Edge 10 t

Output Data Hold after Clock Rising Edge 2 t

-10 12 t

CLCL

-133 ns

CLCL

-70 ns

CLCL

+10 ns

CLCL

Input Data Hold after Clock Rising Edge 0 ns

Clock Rising Edge to Input Data Valid 10 t

0 1 2 3 4 5 6 7 8

T

XLXL

T

T

QVXH

XHQX

0 1 2 3 4 5 6 7

T

T

XHDV

XHDX

VALIDVALIDVALID

VALID VALID

-133 ns

CLCL

SET TI

VALID VALID VALID

SET RI

Figure 9. Serial Port Timing Waveforms

8.0 EXTERNAL CLOCK DRIVE TIMING CHARACTERISTICS

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

1/t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

Note:

1. Guaranteed, but not tested.

0.45 V

Oscillator Frequency 20 MHz
High Time 16 ns

Low Time 16 ns

Rise Time 20 ns

Fall Time 20 ns

VDD - 0.5

0.7 V

DD

0.2 VDD - 0.1

t

CHCL

t

CHCX

t

CLCL

t

CHCX

t

CLCH

Figure 10. External Clock Drive Timing Waveforms

12

9.0 PACKAGING

E

0.595+0.010

S1

0.005 MIN. TYP.

D

2.000 +0.025

S2

0.005 MIN. typ.
e

0.100

b

0.018 +0.002

PIN 1 I.D.
(Geometry OPTIONAL)

TOP VIEW

C

0.010

END VIEW

+ 0.002

- 0.001

0.600

A

0.185 MAX.

Notes:

1. All package finishes are per MIL-PRF-38535.

2. Letter designations are for cross-reference MIL-STD-1835.

Figure 11. 40-pin Side-Brazed DIP

13

L

0.200

0.125

SIDE VIEW

C

Notes:

1. All exposed metalized areas to be plated per MIL-PRF-38535.

2. Dimension letters refer to MIL-STD-1835.

Figure 12. 44-Lead Flatpack

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APPENDIX A

Difference Between Industry Standard and UT69RH051

The areas in which the UT69RH051 differs from the industry
standard will be covered in this section. In this discussion,
industry standard will be used generically to refer to all speed
grades including the 20MHz.

1.0 RESET

The UT69RH051 requires the RST input to be held high for at
least 24 oscillator periods to guarantee the reset is completed in
the chip. Also, the port pins are reset asynchronously as soon as
the RST pin is pulled high. On the UT69RH051 all portions of
the chip are reset synchronously when the RST pin is high during
a rising edge of the input clock. When coming out of reset, the
industry standard takes 1 to 2 machine cycles to begin driving
ALE and PSEN immediately after the RST is removed, but the
access during the first machine cycle after reset is ignored by the
processor. The second cycle will repeat the access and processing
will begin.

2.0 POWER SAVING MODES OF OPERATION

2.1 Idle Mode

Idle mode and the corresponding control bit in the PCON SFR
have not been implemented in the UT69RH051. Setting the idle
control bit has no effect.

2.2 Power Down Mode

Power down mode and the corresponding control bit in the PCON
register have not been implemented in the UT69RH051. Setting
the power down control bit has no effect. Also, the Power Off
Flag in the PCON has not been implemented.

3.0 ON CIRCUIT EMULATION

The On Circuit Emulation mode of operation in the industry
standard has not been implemented in the UT69RH051.

4.0 OPERATING CONDITIONS

The operating voltage range for the industry standard is
5V+20%. The operating temperature range is 0°C to 70°C. On
the UT69RH051, the operating voltage range is 5V+10%. The
operating temperature range is -55°C to +125 °C.

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APPENDIX B

Impact of External Program ROM

The 8051 family of microcontrollers, including the industry
standards, use ports 0 and 2 to access external memory. In
implementations with external program memory, these two ports

are dedicated to the program ROM interface and can not be used
as Input/Output ports. The UT69RH051 uses external program
ROM, so ports 0 and 2 will not be available for I/O.

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ORDERING INFORMATION

UT69RH051 Microcontroller: SMD

5962 * 95638 * * * *

Lead Finish:
(A) = Solder
(C) = Gold

(X) = Optional

Case Outline:
(Q) = 40-pin DIP
(Y) = 44-pin Flatpack

Class Designator:
(Q) = Class Q
(V) = Class V

Device Type
(01) = 8-bit Microcontroller

Drawing Number: 95638

Total Dose:
(H) = 1E6 rads(Si)
(G) = 5E5 rads(Si)
(F) = 3E5 rads(Si)
(R) = 1E5 rads(Si)

Federal Stock Class Designator: No options

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.

17

UT69RH051 Microcontroller

UT **** *** - * * * *

Total Dose:
( ) = None

Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional

Screening:
(C) = Mil Temp
(P) = Prototype

Package Type:
(P) = 40-pin DIP
(W) = 44-pin Flatpack

Device Type:
(UT69RH051) = 8-bit Microcontroller

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Radiation characteristics are neither tested nor guaranteed and may not be specified.

4. Devices have prototype assembly and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed and may not be specified.

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