Datasheet 5962R0153501VXX, 5962R0153501VXC, 5962R0153501VXA, 5962R0153501QXX, 5962R0153501QXC Datasheet (UTMC)

1

FEATURES

q 15 to 50MHz shift clock support
q 50% duty cycle on receiver output clock
q Low power consumption
q Cold sparing all pins
q +1V common mode range (around +1.2V)
q Narrow bus reduces cable size and cost
q Up to 1.05 Gbps throughput
q Up to 132 Megabytes/sec bandwidth
q 325 mV (typ) swing LVDS devices for low EMI
q PLL requires no external components
q Rising edge strobe
q Radiation-hardened design; total dose irradiation testing to

MIL-STD-883 Method 1019

- Total-dose: 300 krad(Si) and 1 Mrad(Si)

- Latchup immune (LET > 100 MeV-cm2/mg)

q Packaging options:

- 48-lead flatpack

q Standard Microcircuit Drawing 5962-01535

- QML Q and V compliant part

q Compatible with TIA/EIA-644 LVDS standard

INTRODUCTION

The UT54LVDS218 Deserializer converts the three LVDS data
streams back into 21 bits of CMOS/TTL data. At a transmit clock
frequency of 50MHz, 21 bits of TTL data are transmitted at a
rate of 350 Mbps per LVDS data channel. Using a 50 MHz clock,
the data throughput is 1.05 Gbit/s (132 Mbytes/sec).

The UT54LVDS218 Deserializer allows the use of wide, high
speed TTL interfaces while reducing overall EMI and cable size.

All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.

Standard Products

UT54LVDS218 Deserializer

Data Sheet

October 2002

LVDS TO-PARALLEL TTL

PLL

POWER DOWN

CMOS/TTL OUTPUTS

21

DATA (LVDS)

CLOCK (LVDS)

RECEIVER CLOCK OUT

Figure 1. UT54LVDS218 Deserializer Block Diagram

2

PIN DESCRIPTION

Notes:

1. These receivers have input fail-safe bias circuitry to guarantee a stable receiver
output for floating or terminated receiver inputs. Under these conditions receiver
inputs will be in a HIGH state. If a clock signal is present, outputs will all be
HIGH; if the clock input is also floating/terminated outputs will remain in the
last valid state. A floating/terminated clock input will result in a LOW clock
output.

Figure 2. UT54LVDS218 Pinout

UT54LVDS218

48
47

46

45
44

43

42
41

V

DD

1RxOUT 17

2

3
4

5
6
7

8RxIN0­9

10
11

12
13
14

15
16

GND

N/C

LVDS GND

LVDS V

DD

LVDS GND

RxCLK IN-

17
18
19

20
21
22
23

24

LVDS GND

PLL V

DD

RxCLK OUT

RxOUT0

V

DD

GND

40

39
38

37
36
35

34
33

V

DD

RxOUT 6

GND

RxOUT 9

32

31
30

29

28
27
26

25

GND

GND

V

DD

RxOUT 18

RxOUT 19
RxOUT 20

RxIN0+

RxIN1-

RxIN1+

RxIN2-

RxIN2+

RxCLK IN+

PLL GND

PLL GND

PWR DWN

RxOUT 16
RxOUT 15

RxOUT 14

RxOUT 13

RxOUT 12
RxOUT 11

RxOUT 10

RxOUT 8

RxOUT 7

RxOUT 3

RxOUT 5
RxOUT 4

RxOUT 2
RxOUT 1

Pin Name I/O No.

Description

RxIN+ I 3

Positive LVDS differential data inputs

1

RxIN- I 3

Negative LVDS differential data output

1

RxOUT O 21

TTL level data outputs

RxCLK IN+ I 1

Positive LVDS differential clock input

RxCLK IN- I 1

Negative LVDS differential clock input

RxCLK OUT O 1

TTL level clock output. The rising edge acts
as data strobe. Pin name RxCLK OUT.

PWR DWN I 1

TTL level input. When asserted (low input)
the receiver outputs are low

V

DD

I 4

Power supply pins for TTL outputs and log­ic

GND I 5

Ground pins for TTL outputs and logic

PLL V

DD

I 1

Power supply for PLL

PLL GND I 2

Ground pin for PLL

LVDS V

DD

I 1

Power supply pin for LVDS pins

LVDS GND I 3

Ground pins for LVDS inputs

TxIN

TX

0
1
2

CMOS/
TTL

18
19
20

TxCLK

PCB

RxOUT

RX

0
1
2

18
19
20

RxCLK

PCB

SHIELD

GND

CLOCK
(LVDS)

DATA
(LVDS)

LVDS CABLE

MEDIA DEPENDENT

Figure 3. UT54LVDS218 Typical Application

3

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3. Test per MIL-STD-883, Method 1012.

4. For cold spare mode (VDD = VSS), V

I/O

may be -0.3V to the maximum recommended operating VDD +0.3V.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD

DC supply voltage -0.3 to 4.0V

V

I/O

Voltage on any pin -0.3 to (VDD + 0.3V)

T

STG

Storage temperature -65 to +150°C

P

D

Maximum power dissipation 1.25 W

T

J Maximum junction temperature

2

+150°C

Θ

JC

Thermal resistance, junction-to-case

3

10°C/W

I

I

DC input current

±10mA

SYMBOL PARAMETER LIMITS

V

DD

Positive supply voltage 3.0 to 3.6V

T

C

Case temperature range -55 to +125°C

V

IN

DC input voltage 0V to V

DD

4

DC ELECTRICAL CHARACTERISTICS

1

(VDD = 3.0V to 0.3V ; -55°C < TC < +125°C)

Notes:

1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenc ed to ground.

2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed
maximum junction temperature specification.

3. Guaranteed by characterization.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

CMOS/TTL DC SPECIFICATIONS (PWR DWN, RXOUT)

V

IH

High-level input voltage 2.0 V

DD

V

V

IL

Low-level input voltage GND 0.8 V

V

OL

Low-level output voltage IOL = 2mA 0.3 V

V

OH

High-level output voltage IOL = -0.4mA 2.7 V

I

IH

High-level input current VIN=3.6V; VDD = 3.6V -10 +10 µA

I

IL

Low-level input current VIN=0V; VDD = 3.6V -10 +10 µA

V

CL

Input clamp voltage ICL = -18mA -1.5 V

I

CS

Cold spare leakage current VIN=3.6V; VDD = V

SS

-20 +20 µA

I

OS

2, 3

Output short circuit current V

OUT

= 0V -15 -130 mA

LVDS RECEIVER DC SPECIFICATIONS (IN+, IN-)

V

ΤΗ

3

Differential input high threshold VCM = +1.2V +100 mV

V

ΤL

3

Differential input low threshold VCM = +1.2V -100 mV

V

CMR

Common mode voltage range VID=210mV 0.2 2.00 V

I

IN

Input current VIN = +2.4V, VDD = 3.6V -10 +10 µA

VIN = 0V, VDD = 3.6V -10 +10 µA

I

CSIN

Cold spare leakage current VIN = 3.6V, VDD = V

SS

-20 +20 µA

Supply Current

I

CC

3

Active supply current CL=8pF (see Figure 4) 105 mΑ

I

CCPD

Power down supply current PWR DWN = Low, LVDS inputs =

logic low

2.0 mA

5

RECEIVER SWITCHING CHARACTERISTICS

1

(VDD = 3.0V to 3.6V; TA = -55°C to +125°C)

Notes:

1. Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and
max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), and source clock jitter less than 250 ps (calculated from T

POS

- R

POS

) - see Figure 11.

2. Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for
LVDS217 Serializer and the LVDS218 Deserializer is (T + TCCD) + 2*T + RCCD), where T = Clock period.

3. Guaranteed by characterization.

4. Guaranteed by design.

SYMBOL PARAMETER MIN MAX UNIT

CLHT

3

CMOS/TTL Low-to-High Transition Time (Figure 5) 3.5 ns

CHLT

3

CMOS/TTL High-to-Low Transition Time (Figure 5) 3.5 ns

RSPos0

3

Receiver Input Strobe Position for Bit 0 (Figure 10) 0.59 1.33 ns

RSPos1

3

Receiver Input Strobe Position for Bit 1 (Figure 10) 3.45 4.19 ns

RSPos2

3

Receiver Input Strobe Position for Bit 2 (Figure 10) 6.30 7.04 ns

RSPos3

3

Receiver Input Strobe Position for Bit 3 (Figure 10) 9.16 9.90 ns

RSPos4

3

Receiver Input Strobe Position for Bit 4 (Figure 10)

12.02

12.76 ns

RSPos5

3

Receiver Input Strobe Position for Bit 5 (Figure 10) 14.88 15.62 ns

RSPos6

3

Receiver Input Strobe Position for Bit 6(Figure 10) 17.73 18.47 ns

RCOP

3

RxCLK OUT Period (Figure 6) 20.00 66.7 ns

RCOH

3

RxCLK OUT High Time (Figure 6) 3.6 ns

RCOL

3

RxCLK OUT Low Time (Figure 6) 3.6 ns

RSRC

4

RxOUT Setup to RxCLK OUT (Figure 6) 3.5 ns

RHRC

4

RxOUT Hold to RxCLK OUT (Figure 6) 3.5 ns

RCCD

2

RxCLK IN to RxCLK OUT Delay (Figure 7) 3.4 8.3 ns

RRLLS Receiver Phase Lock Loop Set (Figure 8) 10 ms

RPDD Receiver Powerdown Delay (Figure 9) 2 µs

f=50MHz
f=50MHz

f=50MHz

f=50MHz
f=50MHz

f=50MHz

f=50MHz

f=50MHz

f=50MHz

f=50MHz

f=50MHz
f=50MHz

6

RxCLK OUT

ODD Rx OUT

Figure 4. Test Pattern

T

EVEN Rx OUT

7

AC TIMING DIAGRAMS

80%

CLHT CHLT

CMOS/TTL OUTPUT

20%

80%

20%

CMOS/TTL OUTPUT

8pF

Figure 5. UT54LVDS218 Output Load and Transition Times

RCOH

RCOP

RCOL

RxCLK OUT

VDD/2 VDD/2

RSRC RHRC

RxOUT 0:20

Figure 6. UT54LVDS218 Setup/Hold and High/Low Times

VDD/2

RxCLK IN

Vdiff=
0V

RxCLK OUT

RCCD

VDD/2

Figure 7. UT54LVDS218 Clock-to-Clock Out Delay

-

+

VDD/2 VDD/2

8

POWER DOWN

V

DD

RPLLS

RxCLK IN

RxCLK OUT

VDD/2

VDD/2

Figure 8. UT54LVDS218 Phase Lock Loop Set Time

POWER DOWN

RxCLK OUT

RxCLKIN

RPDD

VDD/2

Figure 9. Receiver Powerdown Delay

Low

VDD/2

9

RxCLK IN/

Differential

Previous Cycle Next Cycle

RxIN0

RxIN1

RxIN2

RSPos0 MIN

RSPos0 MAX

RSPos1 MIN

RSPos1 MAX

RSPos2 MIN

RSPos2 MAX

RSPos3 MIN

T

CLK

RSPos3 MAX

RSPos4 MIN

RSPos4 MAX

RSPos5 MIN

RSPos5 MAX

RSPos6 MIN

RSPos6 MAX

Figure 10. Receiver LVDS Input Strobe Position

10

RxIN+ or RxIN-

Ideal Strobe Position

RxIN- or RxIN+

C

MIN MAX MIN MAXMIN MAX

RSKM RSKM

Tpposn Rsposn Tpposn+1

~1.4V

~1.0V

C - Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input stroke position min and max
Tspos - Transmitter output pulse position (min and max)

RSKM > Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)1 + ISI (Inter-symbol interference)2
Cable Skew - typically 10 ps-40 ps per foot, media dependent

Notes:

1. Cycle-to-cycle jitter is less than 250 ps at 50MHz.

2. ISI is dependent on interconnect length, may be zero.

Figure 11. Receiver LVDS Skew Margin

11

PACKAGING

1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.

2. The lid is electrically connected to VSS.

3. Lead finishes are in accordance with MIL-PRF-38535.

4. Lead position and colanarity are not measured.

5. ID mark symbol is vendor option.

6. With solder, increase maximum by 0.003.

7. Package dimensions and symbols are similar to MIL-STD-1835 variation F-19.

Figure 12. 48-Lead Flatpack

12

ORDERING INFORMATION

UT54LVDS218 Deserializer:

UT 54LVDS218 - * * * * *

Device Type:
UT54LVDS218 Deserializer

Access Time:
Not applicable

Package Type:
(U) = 48-lead Flatpack (dual-in-line)

Screening:
(C) = Military Temperature Range flow
(P) = Prototype flow

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither

tested nor guaranteed.

4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.

Radiation neither tested nor guaranteed.

13

UT54LVDS218 Deserializer: SMD

5962 -

* * *

Federal Stock Class Designator: No Options

Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)

Drawing Number: 01535

Device Type
01 = LVDS Deserializer

Class Designator:
(Q) = QML Class Q
(V) = QML Class V

Case Outline:
(X) = 48-lead Flatpack

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)

01535

**

Notes:

1.Lead finish (A,C, or X) must be specified.

2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.