Page 1
SN54CBT3383, SN74CBT3383
10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003J – NOVEMBER 1992 – REVISED MAY 1999
D
Functionally Equivalent to QS3383 and
QS3L383
D
5-Ω Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB, DBQ), Thin Very Small-Outline (DGV),
and Thin Shrink Small-Outline (PW)
Packages, Ceramic DIPs (JT), and Ceramic
Flat (W) Package
description
The ’CBT3383 devices provide ten bits of
high-speed TTL-compatible bus switching or
exchanging. The low on-state resistance of the
SN74CBT3383 . . . DB, DBQ, DGV, DW, OR PW PACKAGE
SN54CBT3383 ...JT OR W PACKAGE
(TOP VIEW)
BE
1B1
1A1
1A2
1B2
2B1
2A1
2A2
2B2
3B1
3A1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
5B2
5A2
5A1
5B1
4B2
4A2
4A1
4B1
3B2
3A2
BX
switch allows connections to be made with
minimal propagation delay.
The devices operate as a 10-bit bus switch or a 5-bit bus exchanger, which provides swapping of the A and B
pairs of signals. The bus-exchange function is selected when BX is high. The switches are connected when BE
is low.
The SN54CBT3383 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74CBT3383 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
BE BX 1A1–5A1 1A2–5A2
L L 1B1–5B1 1B2–5B2
L H 1B2–5B2 1B1–5B1
H X Z Z
INPUTS/OUTPUTS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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SN54CBT3383, SN74CBT3383
10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003J – NOVEMBER 1992 – REVISED MAY 1999
logic diagram (positive logic)
1A1
1A2
5A1
5A2
3
4
21
22
20
23
2
1B1
5
1B2
5B1
5B2
1
BE
13
BX
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O
(see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
IK
DBQ package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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UNIT
PARAMETER
TEST CONDITIONS
UNIT
CiControl inputs
pF
C
pF
§
V
0
PARAMETER
UNIT
SN54CBT3383, SN74CBT3383
10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003J – NOVEMBER 1992 – REVISED MAY 1999
recommended operating conditions (see Note 3)
SN54CBT3383 SN74CBT3383
MIN MAX MIN MAX
V
V
V
T
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
I
I
I
CC
∆I
r
on
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
§
Measured by the voltage drop between the input terminal and the output terminal at the indicated current through the switch. On-state resistance
is determined by the lowest voltage of the two (A or B) terminals.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level control input voltage 2 2 V
IH
Low-level control input voltage 0.8 0.8 V
IL
Operating free-air temperature –55 125 0 70 °C
A
Implications of Slow or Floating CMOS Inputs
IK
‡
CC
io(OFF)
Control inputs
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 5.5 V, VI = 5.5 V or GND ±5 ±1 µA
VCC = 5.5 V, IO = 0, VI = VCC or GND 50 50 µA
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 3 V or 0 3
p
VI = 2.5 V 5
VO = 3 V or 0, BE = V
VO = 2.5 V, BE = V
VCC = 4.5 V
VI = 2.4 V, II = 15 mA 10 17 10 15
, literature number SCBA004.
CC
CC
=
I
II = 64 mA 5 9.2 5 7
II = 30 mA 5 7
SN54CBT3383 SN74CBT3383
MIN TYP†MAX MIN TYP†MAX
2.5 2.5 mA
6
p
6
p
Ω
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
¶
t
pd
t
pd
t
en
t
dis
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
A or B B or A 1.5 0.25 ns
BX
BE
BE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A or B 1 10.2 1 9.2 ns
A or B 1 10.8 1 8.6 ns
A or B 1 8.2 1 7.5 ns
SN54CBT3383 SN74CBT3383
MIN MAX MIN MAX
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SN54CBT3383, SN74CBT3383
10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003J – NOVEMBER 1992 – REVISED MAY 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
and t
PLZ
PZL
PLH
and t
and t
PHZ
PZH
PHL
500 Ω
500 Ω
1.5 V 1.5 V
are the same as t
are the same as ten.
are the same as tpd.
dis
.
S1
t
PHL
7 V
GND
3 V
0 V
V
OH
V
OL
Open
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
PLZ
t
PHZ
Open
7 V
Open
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
0 V
Figure 1. Load Circuit and Voltage Waveforms
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Page 5
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Copyright 1999, Texas Instruments Incorporated
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