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54ACTQ16374
16-Bit D Flip-Flop with TRI-STATE
®
Outputs
General Description
The ’ACTQ16374 contains sixteen non-inverting D flip-flops
with TRI-STATEoutputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
The ’ACTQ16245 utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series
®
features GTO
®
output control for superior performance.
Features
n Utilizes NSC FACT Quiet Series technology
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Buffered Positive edge-triggered clock
n Separate control logic for each byte
n 16-bit version of the ’ACTQ374
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-9452801
Logic Symbol
Pin Description
Pin Description
Names
OE
n
Output Enable Input (Active Low)
CP
n
Clock Pulse Input
I
0–I15
Inputs
O
0–O15
Outputs
Connection Diagram
GTO™is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
™
and FACT Quiet Series™are trademarks of Fairchild Semiconductor Corporation.
DS010935-1
Pin Assignment for
CERPAK
DS010935-2
September 1998
54ACTQ16374 16-Bit D Flip-Flop with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS010935 www.national.com
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Functional Description
The ’ACTQ16374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and TRI-STATE true
outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP
n
)
transition. With the Output Enable (OE
n
) LOW, the contents
of the flip-flops are available at the outputs. When OEnis
HIGH, the outputs go to the high impedance state. Operation
of the OE
n
input does not affect the state of the flip-flops.
Truth Tables
Inputs Outputs
CP
1
OE
1
I0–I
7
O0–O
7
NL H H
NL L L
L L X (Previous)
XH X Z
Inputs Outputs
CP
2
OE
2
I8–I
15
O8–O
15
NL H H
NL L L
L L X (Previous)
XH X Z
H
=
High Voltage Level
L=Low Voltage Level
X=Immaterial
Z=High Impedance
Logic Diagrams
Byte 1 (0:7)
DS010935-3
Byte 2 (8:15)
DS010935-4
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+ 0.5V +20 mA
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+ 0.5V
DC Output Source/Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin
±
50 mA
Junction Temperature
CDIP +175˚C
Storage Temperature −65˚C to +150˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
’ACTQ 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA):
54ACTQ −55˚C to +125˚C
Minimum Input Edge Rate (dV/dt)
’ACTQ Devices 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
™
circuits outside databook specifications.
DC Electrical Characteristics for ’ACTQ Family Devices
Symbol Parameter V
CC
(V)
54ACTQ Units Conditions
T
A
=
−55˚C
to +125˚C
Guaranteed Limits
V
IH
Minimum High 4.5 2.0 V V
OUT
=
0.1V
Input Voltage 5.5 2.0 or V
CC
− 0.1V
V
IL
Maximum Low 4.5 0.8 V V
OUT
=
0.1V
Input Voltage 5.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High 4.5 4.4 V I
OUT
=
−50 µA
Output Voltage 5.5 5.4
(Note 2)
V
IN
=
V
IL
or V
IH
4.5 3.70 V I
OH
=
−24 mA
5.5 4.70 I
OH
=
−24 mA
V
OL
Maximum Low 4.5 0.1 V I
OUT
=
50 µA
Output Voltage 5.5 0.1
(Note 2)
V
IN
=
V
IL
or V
IH
4.5 0.50 V I
OL
=
24 mA
5.5 0.50 I
OL
=
24 mA
I
OZ
Maximum TRI-STATE 5.5
±
10.0 µA V
I
=
V
IL,VIH
Leakage Current V
O
=
V
CC
, GND
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
I
CCT
Maximum ICC/Input 5.5 1.6 mA V
I
=
V
CC
− 2.1V
I
CC
Max Quiescent 5.5 160.0 µA V
IN
=
V
CC
Supply Current or GND (Note 6)
I
OLD
(Note 3)
Minimum Dynamic
5.5
50 mA V
OLD
=
1.65V Max
I
OHD
Output Current 50 mA V
OHD
=
3.85V Min
V
OLP
Quiet Output 5.0 0.8 V
Maximum Dynamic V
OL
(Notes 4, 5)
V
OLV
Quiet Output 5.0 -0.8 V
Minimum Dynamic V
OL
(Notes 4, 5)
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DC Electrical Characteristics for ’ACTQ Family Devices (Continued)
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 6: I
CC
for 54ACTQ@25˚C is identical to 74ACTQ@25˚C.
AC Electrical Characteristics
Symbol Parameter V
CC
(V)
(Note 7)
54ACTQ Units
T
A
=
−55˚C to +125˚C
C
L
=
50 pF
Min Max
f
max
Maximum Clock 5.0 65 MHz
Frequency
t
PLH
, Propagation Delay 5.0 3.0 10.5 ns
t
PHL
CP to O
n
3.0 10.5
t
PZH
, Output Enable Time 5.0 3.0 10.5 ns
t
PZL
3.0 11.5
t
PHZ
, Output Disable Time 5.0 2.0 9.0 ns
t
PLZ
2.0 9.0
Note 7: Voltage Range 5.0 is 5.0V±0.5V.
AC Operating Requirements
Symbol Parameter V
CC
(V)
(Note 8)
54ACTQ Units
T
A
=
−55˚C to +125˚C
C
L
=
50 pF
Guaranteed Limits
t
S
Setup Time, HIGH or 5.0 3.0 ns
LOW, Input to Clock
t
H
Hold Time, High or 5.0 1.0 ns
LOW, Input to Clock
t
W
CP Pulse Width, 5.0 5.0 ns
HIGH or LOW
Note 8: Voltage Range 5.0 is 5.0V±0.5V.
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
=
5.0V
C
PD
Power Dissipation 95 pF V
CC
=
5.0V
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Physical Dimensions inches (millimeters) unless otherwise noted
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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48-Lead CERPAK
NS Package Number WA48A
54ACTQ16374 16-Bit D Flip-Flop with TRI-STATE Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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