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54ABT574
Octal D-Type Flip-Flop with TRI-STATE
General Description
The ’ABT574 is an octal flip-flop with a buffered common
Clock (CP) and a buffered common Output Enable (OE).The
information presented to the D inputs is stored in the
flip-flops on the LOW-to-HIGH Clock (CP) transition.
The device is functionally identical to the ’ABT374 except for
the pinouts.
Features
n Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to ’ABT374
Ordering Code
Military Package Number Package Description
54ABT574J/883 J20A 20-Lead Ceramic Dual-In-Line
54ABT574W/883 W20A 20-Lead Cerpack
54ABT574E/883 E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
n TRI-STATE outputs for bus-oriented applications
n Output sink capability of 48 mA, source capability of
24 mA
n Guaranteed multiple output switching specifications
n Output switching specified for both 50 pF and 250 pF
loads
n Guaranteed simultaneous switching, noise level and
dynamic threshold performance
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9322001
®
Outputs
54ABT574 Octal D-Type Flip-Flop with TRI-STATE Outputs
July 1998
Connection Diagrams
Pin Assignment for DIP and Flatpak
DS100208-1
FAST®and TRI-STATE®are registered trademarks of NationalSemiconductor Corporation.
Pin Assignment
for LCC
Pin Descriptions
Pin Description
Names
D
0–D7
CP Clock Pulse Input
OE
O
0–O7
Data Inputs
(Active Rising Edge)
TRI-STATE Output Enable
Input (Active LOW)
TRI-STATE Outputs
DS100208-2
© 1998 National Semiconductor Corporation DS100208 www.national.com
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Functional Description
The ’ABT574 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
are in a high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Function Table
Inputs Internal Outputs Function
OE
CP D Q O
H H or L L NC Z Hold
Logic Diagram
Inputs Internal Outputs Function
OE
CP D Q O
H H or L H NC Z Hold
N
H
H
L
L
L L Z Load
N
H H Z Load
N
L L L Data Available
N
H H H Data Available
L H or L L NC NC No Change in Data
L H or L H NC NC No Change in Data
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
=
N
LOW-to-HIGH Transition
NC=No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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DS100208-3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias
Ceramic −55˚C to +175˚C
Pin Potential to Ground Pin −0.5V to +7.0V
V
CC
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output in
the Disabled or Power-Off State −0.5V to 5.5V
in the HIGH State −0.5V to V
Current Applied to Output
in LOW State (Max) twice the rated I
(mA)
OL
Over Voltage Latchup (I/O) 10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military −55˚C to +125˚C
Supply Voltage
Military +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
Clock Input 100 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
CC
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Latchup Source Current −500 mA
DC Electrical Characteristics
Symbol Parameter ABT574 Units V
Min Typ Max
V
Input HIGH Voltage 2.0 V Recognized HIGH Signal
IH
V
Input LOW Voltage 0.8 V Recognized LOW Signal
IL
V
Input Clamp Diode Voltage −1.2 V Min I
CD
V
Output HIGH Voltage 54ABT 2.5 V Min I
OH
V
Output LOW Voltage 54ABT 0.55 V Min I
OL
I
Input HIGH Current 5 µA Max V
IH
I
Input HIGH Current Breakdown Test 7 µA Max V
BVI
I
Input LOW Current −5 µA Max V
IL
V
Input Leakage Test 4.75 V 0.0 I
ID
I
Output Leakage Current 50 µA 0 − 5.5V V
OZH
I
Output Leakage Current −50 µA 0 − 5.5V V
OZL
I
Output Short-Circuit Current −100 −275 mA Max V
OS
I
Output High Leakage Current 50 µA Max V
CEX
I
Bus Drainage Test 100 µA 0.0 V
ZZ
I
Power Supply Current 50 µA Max All Outputs HIGH
CCH
I
Power Supply Current 30 mA Max All Outputs LOW
CCL
I
Power Supply Current 50 µA Max OE=V
CCZ
I
Additional ICC/Input Outputs Enabled 2.5 mA V
CCT
Outputs TRI-STATE 2.5 mA Max Enable Input V
Outputs TRI-STATE 2.5 mA Data Input V
I
CCD
Dynamic I
CC
No Load mA/ Max Outputs Open, OE=GND,
(Note 4) 0.30 MHz One Bit Toggling (Note 3),
Note 3: For 8-bit toggling, I
Note 4: Guaranteed, but not tested.
CCD
<
0.8 mA/MHz.
54ABT 2.0 V Min I
5V
−5 V
CC
=
−18 mA
IN
=
−3 mA
OH
=
−24 mA
OH
=
48 mA
OL
=
2.7V (Note 4)
IN
=
V
IN
CC
=
7.0V
IN
=
0.5V (Note 4)
IN
=
0.0V
IN
=
1.9 µA
ID
All Other Pins Grounded
=
2.7V; OE=2.0V
OUT
=
0.5V; OE=2.0V
OUT
=
0.0V
OUT
=
V
OUT
=
5.5V; All Other GND
OUT
CC
All Others at VCCor GND
=
V
I
CC
All Others at V
50%Duty Cycle
Conditions
CC
− 2.1V
=
I
=
V
I
CC
V
CC
− 2.1V
CC
or GND
− 2.1V
3 www.national.com
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AC Electrical Characteristics
54ABT
=
T
−55˚C to +125˚C
A
Symbol Parameter V
=
4.5V to 5.5V Units
CC
=
C
50 pF
L
Min Max
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Max Clock Frequency 150 MHz
Propagation Delay 1.5 7.0 ns
CP to O
n
1.5 7.4
Output Enable Time 1.0 6.5 ns
1.0 7.2
Output Disable Time 1.0 7.2 ns
1.0 6.7
AC Operating Requirements
54ABT
=
T
−55˚C to +125˚C
A
Symbol Parameter V
Min Max
t
(H) Setup Time, HIGH 1.5 ns
s
t
(L) or LOW Dnto CP 2.0
s
t
(H) Hold Time, HIGH 2.0 ns
h
t
(L) or LOW Dnto CP 2.0
h
t
(H) Pulse Width, CP, 3.3 ns
w
t
(L) HIGH or LOW 3.3
w
=
4.5V to 5.5V Units
CC
=
C
50 pF
L
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
C
(Note 5) Output Capacitance 9.0 pF V
Note 5: C
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OUT
is measured at frequency f=1 MHz, per MIL-STD-883B, Method 3012.
OUT
T
vs Temperature (TA)C
PHL
1 Output Switching, Clock to Output
Input Capacitance 5.0 pF V
=
50 pF,
L
DS100208-12
=
T
25˚C
A
=
0V
CC
=
5.0V
CC
T
vs Temperature (TA)C
PLH
1 Output Switching, Clock to Output
=
50 pF,
L
DS100208-13
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Capacitance (Continued)
vs Temperature (TA)C
T
PZH
1 Output Switching, OE to Output
T
vs Temperature (TA)C
PHZ
1 Output Switching, OE to Output
T
LOW vs Temperature (TA)C
SET
1 Output Switching, Data to Clock
=
50 pF,
L
DS100208-14
=
50 pF,
L
DS100208-16
=
50 pF,
L
T
vs Temperature (TA)C
PZL
1 Output Switching, OE to Output
T
vs Temperature (TA)C
PLZ
1 Output Switching, OE to Output
T
vs Temperature (TA)C
SET
1 Output Switching, Data to Clock
=
50 pF,
L
DS100208-15
=
50 pF,
L
DS100208-17
=
50 pF,
L
T
HIGH vs Temperature (TA)C
HOLD
1 Output Switching, Data to Clock
DS100208-18
=
50 pF,
L
DS100208-20
T
LOW vs Temperature (TA)C
HOLD
1 Output Switching, Data to Clock
5 www.national.com
DS100208-19
=
50 pF,
L
DS100208-21
Page 6
Capacitance (Continued)
vs Temperature (TA)C
T
PLH
8 Outputs Switching, Clock to Output
T
vs Temperature (TA)C
PZH
8 Outputs Switching, OE to Output
T
vs Temperature (TA)C
PHZ
8 Outputs Switching, OE to Output
=
50 pF,
L
=
50 pF,
L
=
50 pF,
L
DS100208-22
DS100208-24
T
vs Temperature (TA)C
PHL
8 Outputs Switching, Clock to Output
T
vs Temperature (TA)C
PZL
8 Outputs Switching, OE to Output
T
vs Temperature (TA)C
PLZ
8 Outputs Switching, OE to Output
=
50 pF,
L
=
50 pF,
L
=
50 pF,
L
DS100208-23
DS100208-25
DS100208-26
T
vs Load Capacitance T
PLH
1 Output Switching, Clock to Output
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=
25˚C,
A
DS100208-28
T
vs Load Capacitance T
PHL
1 Output Switching, Clock to Output
=
25˚C,
A
DS100208-27
DS100208-29
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Capacitance (Continued)
vs Load Capacitance T
T
PLH
8 Outputs Switching, Clock to Output
T
vs Load Capacitance T
PZH
8 Outputs Switching, OE to Output
T
and T
PLH
C
Outputs In Phase, Clock to Output
vs Number Outputs Switching
PHL
L
=
50 pF, T
A
=
25˚C, V
CC
=
25˚C,
A
DS100208-30
=
25˚C,
A
DS100208-32
=
5.0V,
T
vs Load Capacitance T
PHL
8 Outputs Switching, Clock to Output
T
vs Load Capacitance T
PZL
8 Outputs Switching, OE to Output
Typical ICCvs Output Switching Frequency
=
C
0pF,V
L
1 Output Switching at 50%Duty Cycle
=
CC
=
25˚C,
A
DS100208-31
=
25˚C,
A
DS100208-33
=
V
5.5V,
IH
DS100208-34
DS100208-35
7 www.national.com
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AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100208-4
DS100208-8
FIGURE 2. V
=
1.5V
M
Input Pulse Requirements
Amplitude Rep. Rate t
w
t
r
3.0V 1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100208-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100208-6
t
f
DS100208-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
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DS100208-9
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
Page 9
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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Page 10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
54ABT574 Octal D-Type Flip-Flop with TRI-STATE Outputs
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