Datasheet 5962-9230601VYA, 5962-9230601VXA, 5962-9230601MYA, 5962-9230601MXA, 100336MW8 Datasheet (NSC)
Page 1
100336
Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down
counter or as a 4-bit bidirectional shift register. Three Select
(S
n
) inputsdetermine the mode of operation, as shown in the
Function Select table. Two Count Enable (CEP, CET) inputs
are provided for ease of cascading in multistage counters.
One Count Enable (CET) input also doubles as a Serial Data
(D0) input for shift-up operation. For shift-down operation, D
3
is the Serial Data input. In counting operations the Terminal
Count (TC) output goes LOW when the counter reaches 15
in the count/up mode or 0 (zero) in the count/down mode. In
the shift modes, the TC output repeats the Q
3
output. The
dual nature of this TC/Q3output and the D0/CET input
means that one interconnection from one stage to the next
higher stage serves as the link for multistage counting or
shift-up operation. The individual Preset (P
n
) inputs are used
to enter data in parallel or to preset the counter in programmable counter applications.AHIGH signal on the Master Reset (MR) input overrides all other inputs and asynchronously
clears the flip-flops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50
kΩ pull-down resistors.
Features
n 40%power reduction of the 100136
n 2000V ESD protection
n Pin/function compatible with 100136
n Voltage compensated operating range=−4.2V to −5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9230601
Logic Symbol
Pin
Names
Description
CP Clock Pulse Input
CEP
Count Enable Parallel Input (Active LOW)
D
0
/CET Serial Data Input/Count Enable
Trickle Input (Active LOW)
S
0–S2
Select Inputs
MR Master Reset Input
P
0–P3
Preset Inputs
D
3
Serial Data Input
TC
Terminal Count Output
Q
0–Q3
Data Outputs
Q
0–Q3
Complementary Data Outputs
DS100307-1
August 1998
100336 Low Power 4-Stage Counter/Shift Register
© 1998 National Semiconductor Corporation DS100307 www.national.com
Page 2
Connection Diagrams
24-Pin DIP
DS100307-2
24-Pin Quad Cerpak
DS100307-3
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Logic Diagram
DS100307-5
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Function Select Table
S
2
S
1
S
0
Function
L L L Parallel Load
L L H Complement
L H L Shift Left
L H H Shift Right
H L L Count Down
H L H Clear
H H L Count Up
H H H Hold
Truth Table
Q
0
=
LSB
Inputs Outputs
MR S
2S1S0
CEP D0/CET D3CP Q3Q2Q1Q
0
TC Mode
LLLLX X X
N
P3P2P1P0L Preset (Parallel Load)
LLLHX X X
N
Q3Q2Q1Q0L Invert
LLHL X X X
N
D3Q3Q2Q1D3Shift to LSB
LLHHX X X
N
Q2Q1Q0D0Q3(Note 1) Shift to MSB
LHLL L L X
N
(Q
0–3
) minus 1 1 Count Down
LHLL H L XXQ
3Q2Q1Q0
1 Count Down with CEP not active
LHLL X H XXQ3Q2Q1Q0H Count Down with CET not active
LHLHX X X
N
LLLL H Clear
LHHL L L X
N
(Q
0–3
) plus 1 2 Count Up
LHHLH L XXQ
3Q2Q1Q0
2 Count Up with CEP not active
LHHLX H XXQ3Q2Q1Q0H Count Up with CET not active
LHHH X X XXQ3Q2Q1Q0H Hold
HLLLX X XXLLLL L
HLLHX X XXLLLL L
HLHL X X XXLLLL L
HLHHX X XXLLLL L Asynchronous
HHLLX L XXLLLL L Master Reset
HHLLX H XXLLLL H
HHLHX X XXLLLL H
HHHL X X XXLLLL H
HHHH X X XXLLLL H
1=LifQ0–Q
3
=
LLLL
HifQ
0–Q3
≠
LLLL
2=LifQ
0–Q3
=
HHHH
HifQ
0–Q3
≠
HHHH
H=HIGH Voltage Level
L=LOW Voltage Level
X=Don’t Care
N
=
LOW-to-HIGH Transition
Note 1: Before the clock, TC is Q
3
After the clock, TC is Q
2
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Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature (T
STG
) −65˚C to +150˚C
Maximum Junction Temperature (T
J
)
Ceramic +175˚C
V
EE
Pin Potential to Ground Pin −7.0V to +0.5V
Input Voltage (DC) V
EE
to +0.5V
Output Current (DC Output HIGH) −50 mA
ESD (Note 3) ≥2000V
Recommended Operating
Conditions
Case Temperature (TC)
Military −55˚C to +125˚C
Supply Voltage (V
EE
) −5.7V to −4.2V
Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
=
−4.2V to −5.7V, V
CC
=
V
CCA
=
GND, T
C
=
−55˚C to +125˚C
Symbol Parameter Min Max Units T
C
Conditions Notes
V
OH
Output HIGH Voltage −1025 −870 mV 0˚C to
+125˚C V
IN
=
V
IH (Max)
Loading with
−1085 −870 mV −55˚C or V
IL (Min)
50Ω to −2.0V (Notes 4, 5, 6)
V
OL
Output LOW Voltage −1830 −1620 mV 0˚C to
+125˚C
−1830 −1555 mV −55˚C
V
OHC
Output HIGH Voltage −1035 mV 0˚C to
+125˚C V
IN
=
V
IH (Min)
Loading with
−1085 mV −55˚C or V
IL (Max)
50Ω to −2.0V (Notes 4, 5, 6)
V
OLC
Output LOW Voltage −1610 mV 0˚C to
+125˚C
−1555 mV −55˚C
V
IH
Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal (Notes 4, 5, 6, 7)
+125˚C for All Inputs
V
IL
Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal (Notes 4, 5, 6, 7)
+125˚C for All Inputs
I
IL
Input LOW Current 0.50 µA −55˚C to V
EE
=
−4.2V (Notes 4, 5, 6)
+125˚C V
IN
=
V
IL (Min)
I
IH
Input HIGH Current 240 µA 0˚C to V
EE
=
−5.7V
+125˚C V
IN
=
V
IH(Max)
(Notes 4, 5, 6)
340 µA −55˚C
I
EE
Power Supply Current −55˚C Inputs Open
−185 −70 mA to V
EE
=
−4.2V to −4.8V (Notes 4, 5, 6)
−195 −70 +125˚C V
EE
=
−4.2V to −5.7V
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stablize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 5: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.
Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 7: Guaranteed by applying specified input conditon and testing V
OH/VOL
.
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Military Version
AC Characteristics
V
EE
=
−4.2V to −5.7V, V
CC
=
V
CCA
=
GND
Symbol Parameter T
C
=
−55˚C T
C
=
+25˚C T
C
=
+125˚ Units Conditions Notes
Min Max Min Max Min Max
f
shift
Shift Frequency 325 325 325 MHz
Figures 2, 3
(Note 11)
t
PLH
Propagation Delay 0.40 2.30 0.50 2.20 0.40 2.50 ns
Figures 1, 3
t
PHL
CP to Qn,Q
n
(Notes 8, 9, 10, 12)
t
PLH
Propagation Delay 1.30 3.90 1.70 3.80 1.70 4.20 ns
Figures 1, 7, 8
t
PHL
CP to TC (Shift)
t
PLH
Propagation Delay 1.20 4.60 1.50 4.60 1.60 5.20 ns
Figures 1, 9
(Notes 8, 9, 10, 12)
t
PHL
CP to TC (Count)
t
PLH
Propagation Delay 0.60 2.90 0.80 2.80 0.90 3.20 ns
Figures 1, 4
t
PHL
MR to Qn,Q
n
(Notes 8, 9, 10, 12)
t
PLH
Propagation Delay 2.30 5.20 2.70 5.20 2.90 5.90 ns
Figures 1, 12
t
PHL
MR to TC (Count)
t
PHL
Propagation Delay 2.10 4.30 2.20 4.10 2.40 4.70 ns
Figures 1, 10, 11
(Notes 8, 9, 10, 12)
MR to TC (Shift)
t
PLH
Propagation Delay 0.70 3.20 1.00 3.20 1.30 4.10 ns
t
PHL
D0/CET to TC
Figures 1, 5
(Notes 8, 9, 10, 12)
t
PLH
Propagation Delay 1.30 4.10 1.50 4.20 1.70 4.90 ns
t
PHL
Snto TC
t
TLH
Transition Time 0.20 1.90 0.20 1.80 0.20 2.00 ns
Figures 1, 3
(Note 11)
t
THL
20%to 80%,80%to
20
%
t
s
Setup Time
D
3
1.40 1.40 1.40
P
n
1.70 1.70 1.70
D
0
/CET 1.80 1.80 1.80 ns
Figure 6
(Note 11)
CEP
1.80 1.80 1.80
S
n
3.30 3.30 3.30
MR (Release Time) 2.60 2.60 2.60
t
h
Hold Time
D
3
0.90 0.90 0.90
P
n
1.00 1.00 1.00 ns
Figure 6
(Note 11)
D
0
/CET 0.70 0.70 0.70
CEP
0.60 0.60 0.60
S
n
0.00 0.00 0.00
t
pw
(H)
Pulse Width
HIGH: CP
1.60 1.60 1.60
ns
Figures 3, 4
(Note 11)
MR 2.00 2.00 2.00
Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold tempertures.
Note 9: Screen tested 100%on each device at +25˚C temperature only, Subgroups A9.
Note 10: Sample tested (Method 5005, TableI)oneachmanufactured lot at +25˚C, SubgroupsA9,andat+125˚Cand−55˚Ctemperatures,SubgroupsA10andA11.
Note 11: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).
Note 12: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
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Test Circuitry
DS100307-6
Notes:
V
CC,VCCA
=
+2V, V
EE
=
−2.5V
L1, L2 and L3=equal length 50Ω impedance lines
R
T
=
50Ω terminator internal to scope
Decoupling 0.1 µF from GND to V
CC
and V
EE
All unused outputs are loaded with 50Ω to GND
C
L
=
Fixture and stray capacitance ≤ 3pF
Pin numbers shown are for flatpak;
for DIP see logic symbol
FIGURE 1. AC Test Circuit
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Test Circuitry (Continued)
Switching Waveforms
DS100307-7
Notes:
For shift right mode, +1.05V is applied at S
0
.
The feedback path from output to input should be as short as possible.
FIGURE 2. Shift Frequency Test Circuit (Shift Left)
DS100307-8
FIGURE 3. Propagation Delay (Clock) and Transition Times
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Switching Waveforms (Continued)
DS100307-9
FIGURE 4. Propagation Delay (Reset)
DS100307-10
FIGURE 5. Propagation Delay (Serial Data, Selects)
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Switching Waveforms (Continued)
DS100307-11
Notes:
t
s
is the minimum time before the transition of the clock that information must be present at the data input.
t
h
is the minimum time after the transition of the clock that information must remain unchanged at the data input.
FIGURE 6. Setup and Hold Time
DS100307-15
Note: Shift Right Mode; S
0
=
H, S
1
=
H, S
2
=
L.
FIGURE 7. Propagation Delay, Clock to Terminal Count (Shift Right Mode)
DS100307-16
Note: Shift Left Mode; S
0
=
L, S
1
=
H, S
2
=
L.
FIGURE 8. Propagation Delay, Clock to Terminal Count (Shift Left Mode)
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Switching Waveforms (Continued)
DS100307-17
Note:
*
Decimal representation of binary outputs.
Count Up: S
0
=
L, S
1
=
H, S
2
=
H; Count Down: S
0
=
L, S
1
=
L, S
2
=
H.
Measurement taken at 50%point of waveform.
FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes)
DS100307-18
Note: Shift Right Mode; S
0
=
H, S
1
=
H, S
2
=
L.
FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode)
DS100307-19
Note: Shift Left Mode; S
0
=
L, S
1
=
H, S
2
=
L.
FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode)
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Switching Waveforms (Continued)
Applications
DS100307-20
Note:
*
Decimal representation of binary outputs. Count Up Mode: S
0
=
L, S
1
=
H, S
2
=
H.
DS100307-21
Note:
*
Decimal representation of binary outputs. Count Down Mode: S
0
=
L, S
1
=
L, S
2
=
H.
FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes)
3-Stage Divider, Preset Count Down Mode
DS100307-12
Note: If S
0
=
S
1
=
S
2
=
LOW, then T
C
=
LOW
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Applications (Continued)
Slow Expansion Scheme
DS100307-13
Fast Expansion Scheme
DS100307-14
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)
NS Package Number J24E
24-Lead Quad Cerpak (F)
NS Package Number W24B
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LIFE SUPPORT POLICY
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with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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device or system whose failure to perform can be reasonably expected to cause the failure of the life support
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100336 Low Power 4-Stage Counter/Shift Register
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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