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TL/F/9525
54F/74F377 Octal D Flip-Flop with Clock Enable
May 1995
54F/74F377
Octal D Flip-Flop with Clock Enable
General Description
The ’F377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE
) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE
input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable operation.
Features
Y
Ideal for addressable register applications
Y
Clock enable for address and data synchronization
applications
Y
Eight edge-triggered D flip-flops
Y
Buffered common clock
Y
See ’F273 for master reset version
Y
See ’F373 for transparent latch version
Y
See ’F374 for TRI-STATEÉversion
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F377PC N20A 20-Lead (0.300×Wide) Molded Dual-In-Line
54F377DM (QB) J20A 20-Lead Ceramic Dual-In-Line
74F377SC (Note 1) M20B 20-Lead (0.300×Wide) Molded Small Outline, JEDEC
74F377SJ (Note 1) M20D 20-Lead (0.300×Wide) Molded Small Outline, EIAJ
54F377FM (QB) W20A 20-Lead Cerpack
54F377LM (QB) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.
Logic Symbols
TL/F/9525– 1
IEEE/IEC
TL/F/9525– 4
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Page 2
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
TL/F/9525– 2
Pin Assignment
for LCC
TL/F/9525– 3
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
D0–D
7
Data Inputs 1.0/1.0 20 mA/b0.6 mA
CE
Clock Enable (Active LOW) 1.0/1.0 20 mA/b0.6 mA
CP Clock Pulse Input 1.0/1.0 20 mA/
b
0.6 mA
Q0–Q
7
Data Outputs 50/33.3
b
1 mA/20 mA
Mode Select-Function Table
Operating Mode
Inputs Output
CP CE D
n
Q
n
Load ‘‘1’’ L Ih H
Load ‘‘0’’ L II L
Hold L h X No Change
(Do Nothing) X H X No Change
HeHIGH Voltage Level
h
e
HIGH Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
L
e
LOW Voltage Level
I
e
LOW Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
X
e
Immaterial
L
e
LOW-to-HIGH Clock Transition
Logic Diagram
TL/F/9525– 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Page 3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b
65§Ctoa150§C
Ambient Temperature under Bias
b
55§Ctoa125§C
Junction Temperature under Bias
b
55§Ctoa175§C
Plastic
b
55§Ctoa150§C
V
CC
Pin Potential to
Ground Pin
b
0.5V toa7.0V
Input Voltage (Note 2)
b
0.5V toa7.0V
Input Current (Note 2)
b
30 mA toa5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0.5V to V
CC
TRI-STATE Output
b
0.5V toa5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55§Ctoa125§C
Commercial 0
§
Ctoa70§C
Supply Voltage
Military
a
4.5V toa5.5V
Commercial
a
4.5V toa5.5V
DC Electrical Characteristics
Symbol Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1.2 V Min I
IN
eb
18 mA
V
OH
Output HIGH 54F 10% V
CC
2.5 I
OH
eb
1mA
Voltage 74F 10% V
CC
2.5 V Min I
OH
eb
1mA
74F 5% V
CC
2.7 I
OH
eb
1mA
V
OL
Output LOW 54F 10% V
CC
0.5
V Min
I
OL
e
20 mA
Voltage 74F 10% V
CC
0.5 I
OL
e
20 mA
I
IH
Input HIGH Current 5.0 mA Max V
IN
e
2.7V
I
BVI
Input HIGH Current
7.0 mA Max
V
IN
e
7.0V
Breakdown Test
I
IL
Input LOW Current
b
0.6 mA Max V
IN
e
0.5V
I
OS
Output Short-Circuit Current
b
60
b
150 mA Max V
OUT
e
0V
I
CEX
Output HIGH Leakage Current 50 mA Max V
OUT
e
V
CC
V
ID
Input Leakage Test
4.75 V 0.0
I
ID
e
1.9 mA
All Other Pins Grounded
I
OD
Output Leakage Circuit Current
3.75 mA 0.0
V
IOD
e
150 mV
All Other Pins Grounded
I
CCH
Power Supply Current 35 46
mA Max
CPeL
I
CCL
44 56 D
n
eMRe
HIGH
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AC Electrical Characteristics
74F 54F 74F
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com
Symbol Parameter V
CC
ea
5.0V
C
L
e
50 pF C
L
e
50 pF
Units
C
L
e
50 pF
Min Typ Max Min Max Min Max
f
Max
Maximum Clock Frequency 130 85 105 MHz
t
PLH
Propagation Delay 3.0 7.0 2.0 8.5 2.5 7.5
ns
t
PHL
CP to Q
n
4.0 9.0 3.0 10.5 3.5 9.0
AC Operating Requirements
74F 54F 74F
Symbol Parameter
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com Units
V
CC
ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 3.0 3.5 3.0
ns
t
s
(L) Dnto CP 3.5 4.0 3.5
th(H) Hold Time, HIGH or LOW 0.5 1.0 0.5
ns
t
h
(L) Dnto CP 1.0 1.0 1.0
ts(H) Setup Time, HIGH or LOW 4.1 4.0 4.1
ns
t
s
(L) CE to CP 3.5 5.0 4.0
th(H) Hold Time, HIGH to LOW 0.5 1.5 0.5
ns
t
h
(L) CE to CP 2.0 2.5 2.0
tw(H) Clock Pulse Width, 6.0 5.0 6.0
ns
t
w
(L) HIGH or LOW 6.0 5.0 6.0
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
74F 377 S C X
Temperature Range Family Special Variations
74F
e
Commercial XeDevices shipped in 13×reels
54F
e
Military QBeMilitary grade with environmental
and burn-in processing shipped
Device Type
in tubes
Package Code
Temperature Range
P
e
Plastic DIP
C
e
Commercial (0§Ctoa70§C)
D
e
Ceramic DIP
M
e
Military (b55§Ctoa125§C)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
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5
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Physical Dimensions inches (millimeters)
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
20-Lead (0.300×Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M20B
6
Page 7
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)
NS Package Number M20D
7
Page 8
54F/74F377 Octal D Flip-Flop with Clock Enable
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300×Wide) Molded Dual-In-Line Package (P)
NS Package Number N20A
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