Page 1
TL/F/9580
54F/74F646
#
74F646B
#
54F/74F648 Octal Transceiver/Register with TRI-STATE Outputs
December 1994
54F/74F646#74F646B#54F/74F648
Octal Transceiver/Register with TRI-STATE
É
Outputs
General Description
These devices consist of bus transceiver circuits with TRISTATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control G
and direction pins are provided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus will
receive data when the enable control G
is Active LOW. In
the isolation mode (control G
HIGH), A data may be stored
in the B register and/or B data may be stored in the A register.
Features
Y
Independent registers for A and B buses
Y
Multiplexed real-time and stored data
Y
’F648 has inverting data paths
Y
’F646/’F646B have non-inverting data paths
Y
’F646B is a faster version of the ’F646
Y
TRI-STATE outputs
Y
300 mil slim DIP
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F646SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
54F646DM (Note 2) J24F 24-Lead (0.300×Wide) Ceramic Dual-In-Line
74F646SC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC
74F646MSA (Note 1) MSA24 24-Lead Molded Shrink Small Outline, EIAJ, Type II
54F646FM (Note 2) W24C 24-Lead Cerpack
54F646LM (Note 2) E28A 28-Lead Ceramic Leadless Chip Carrier, Type C
74F646BSPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
74F646BSC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC
74F648SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
54F648SDM (Note 2) J24F 24-Lead (0.300×Wide) Ceramic Dual-In-Line
74F648SC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC
54F648FM (Note 2) W24C 24-Lead Cerpack
54F648LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols
’F646/’F646B
TL/F/9580– 1
’F648
TL/F/9580– 7
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Page 2
Logic Symbols (Continued)
IEEE/IEC
’F646/’F646B
TL/F/9580– 4
IEEE/IEC
’F648
TL/F/9580– 9
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
’F646/’F646B
TL/F/9580– 2
Pin Assignment
for LCC
’F646/’F646B
TL/F/9580– 3
Pin Assignment
for DIP, SOIC and Flatpak
’F648
TL/F/9580– 8
Pin Assignment
for LCC
’F648
TL/F/9580– 10
2
Page 3
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
A0–A
7
Data Register A Inputs/ 3.5/1.083 70 mA/b650 mA
TRI-STATE Outputs 600/106.6 (80)
b
12 mA/64 mA (48 mA)
B
0–B7
Data Register B Inputs/ 3.5/1.083 70 mA/b650 mA
TRI-STATE Outputs 600/106.6 (80)b12 mA/64 mA (48 mA)
CPAB, CPBA Clock Pulse Inputs 1.0/1.0 20 mA/
b
0.6 mA
SAB, SBA Select Inputs 1.0/1.0 20 mA/b0.6 mA
G
Output Enable Input 1.0/1.0 20 mA/b0.6 mA
DIR Direction Control Input 1.0/1.0 20 mA/
b
0.6 mA
Function Table
Inputs Data I/O*
Function
G DIR CPAB CPBA SAB SBA A0–A7B0–B
7
H X H or L H or L X X Isolation
HX L X X X Input Input Clock A
n
Data into A Register
HX X L X X Clock B
n
Data into B Register
LH X X L X Anto BnÐReal Time (Transparent Mode)
LH L XLX
Input Output
Clock AnData into A Register
L H H or L X H X A Register to Bn(Stored Mode)
LH L X H X Clock A
n
Data into A Register and Output to B
n
LL X X X L B
n
to AnÐReal Time (Transparent Mode)
LL X L XL
Output Input
Clock B
n
Data into B Register
L L X H or L X H B Register to A
n
(Stored Mode)
LL X L X H Clock B
n
Data into B Register and Output to A
n
*The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus
pins will be stored on every LOW-to-HIGH transition of the clock inputs.
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Irrelevant
L
e
LOW-to-HIGH Transition
3
Page 4
Logic Diagrams (Continued)
’F646/’F646B
TL/F/9580– 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4
Page 5
Logic Diagrams (Continued)
’F648
TL/F/9580– 6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5
Page 6
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b
65§Ctoa150§C
Ambient Temperature under Bias
b
55§Ctoa125§C
Junction Temperature under Bias
b
55§Ctoa175§C
Plastic
b
55§Ctoa150§C
V
CC
Pin Potential to
Ground Pin
b
0.5V toa7.0V
Input Voltage (Note 2)
b
0.5V toa7.0V
Input Current (Note 2)
b
30 mA toa5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0.5V to V
CC
TRI-STATE Output
b
0.5V toa5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55§Ctoa125§C
Commercial 0
§
Ctoa70§C
Supply Voltage
Military
a
4.5V toa5.5V
Commercial
a
4.5V toa5.5V
DC Electrical Characteristics
Symbol Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1.2 V Min I
IN
eb
18 mA (Non I/O Pins)
V
OH
Output HIGH 54F 10% V
CC
2.0
V Min
I
OH
eb
12 mA (An,Bn)
Voltage 74F 10% V
CC
2.0 I
OH
eb
15 mA (An,Bn)
V
OL
Output LOW 54F 10% V
CC
0.55
V Min
I
OL
e
48 mA (An,Bn)
Voltage 74F 10% V
CC
0.55 I
OL
e
64 mA (An,Bn)
I
IH
Input HIGH 54F 20.0
mA Max
V
IN
e
2.7V (Non I/O Pins)
Current 74F 5.0
I
BVI
Input HIGH Current 54F 100
mA Max
V
IN
e
7.0V (Non I/O Pins)
Breakdown Test 74F 7.0
I
BVIT
Input HIGH Current 54F 1.0
mA Max
V
IN
e
5.5V (An,Bn)
Breakdown (I/O) 74F 0.5
I
CEX
Output HIGH 54F 250
mA Max
V
OUT
e
V
CC
Leakage Current 74F 50
V
ID
Input Leakage
74F 4.75 V 0.0
I
ID
e
1.9 mA
Test All Other Pins Grounded
I
OD
Output Leakage
74F 3.75 mA 0.0
V
IOD
e
150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current
b
0.6 mA Max V
IN
e
0.5V (Non I/O Pins)
I
IH
a
I
OZH
Output Leakage Current 70 mA Max V
OUT
e
2.7V (An,Bn)
I
IL
a
I
OZL
Output Leakage Current
b
650 mA Max V
OUT
e
0.5V (An,Bn)
I
OS
Output Short-Circuit Current
b
100
b
225 mA Max V
OUT
e
0V
I
ZZ
Bus Drainage Test 500 mA 0.0V V
OUT
e
5.25V
I
CCH
Power Supply Current 135 mA Max V
O
e
HIGH
I
CCL
Power Supply Current 150 mA Max V
O
e
LOW
I
CCZ
Power Supply Current 150 mA Max V
O
e
HIGH Z
6
Page 7
’F646/’F648
AC Electrical Characteristics
74F 54F 74F
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com
Symbol Parameter V
CC
ea
5.0V
C
L
e
50 pF C
L
e
50 pF
Units
C
L
e
50 pF
Min Max Min Max Min Max
f
max
Maximum Clock Frequency 90 75 90 MHz
t
PLH
Propagation Delay 2.0 7.0 2.0 8.5 2.0 8.0
ns
t
PHL
Clock to Bus 2.0 8.0 2.0 9.5 2.0 9.0
t
PLH
Propagation Delay 1.0 7.0 1.0 8.0 1.0 7.5
ns
t
PHL
Bus to Bus (’F646) 1.0 6.5 1.0 8.0 1.0 7.0
t
PLH
Propagation Delay 2.0 8.5 1.0 10.0 2.0 9.0
ns
t
PHL
Bus to Bus (’F648) 1.0 7.5 1.0 9.0 1.0 8.0
t
PLH
Propagation Delay 2.0 8.5 2.0 11.0 2.0 9.5
ns
t
PHL
SBA or SAB to A or B 2.0 8.0 2.0 10.0 2.0 9.0
t
PZH
Enable Time 2.0 8.5 2.0 10.0 2.0 9.0
ns
t
PZL
OE to A or B 2.0 12.0 2.0 13.5 2.0 12.5
t
PHZ
Disable Time 1.0 7.5 1.0 9.0 1.0 8.5
ns
t
PLZ
OE to A or B 2.0 9.0 2.0 11.0 2.0 9.5
t
PZH
Enable Time 2.0 14.0 2.0 16.0 2.0 15.0
ns
t
PZL
DIR to A or B 2.0 13.0 2.0 15.0 2.0 14.0
t
PHZ
Disable Time 1.0 9.0 1.0 10.0 1.0 9.5
ns
t
PLZ
DIR to A or B 2.0 11.0 2.0 12.0 2.0 11.5
’F646/’F648
AC Operating Requirements
74F 54F 74F
Symbol Parameter
T
A
ea
25
§
C
T
A,VCC
e
Mil TA,V
CC
e
Com Units
V
CC
ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 5.0 5.0 5.0
ns
t
s
(L) Bus to Clock 5.0 5.0 5.0
th(H) Hold Time, HIGH or LOW 2.0 2.5 2.0
ns
t
h
(L) Bus to Clock 2.0 2.5 2.0
tw(H) Clock Pulse Width 5.0 5.0 5.0
ns
t
w
(L) HIGH or LOW 5.0 5.0 5.0
7
Page 8
’F646B
AC Electrical Characteristics
74F 54F 74F
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com
Symbol Parameter V
CC
ea
5.0V
C
L
e
50 pF C
L
e
50 pF
Units
C
L
e
50 pF
Min Max Min Max Min Max
f
max
Maximum Clock Frequency 165 150 MHz
t
PLH
Propagation Delay 2.5 7.0 2.5 8.0
ns
t
PHL
Clock to Bus 3.0 7.5 3.0 8.0
t
PLH
Propagation Delay 2.0 6.0 2.0 7.0
ns
t
PHL
Bus to Bus 2.0 6.0 2.0 7.0
t
PLH
Propagation Delay 2.5 7.5 2.5 8.5
ns
t
PHL
SBA or SAB to A or B 2.5 7.5 2.5 8.5
t
PZH
Enable Time 2.5 6.5 2.5 8.0
ns
t
PZL
OE to A or B 2.5 9.0 2.5 10.0
t
PHZ
Disable Time 1.5 6.5 1.5 7.5
ns
t
PLZ
OE to A or B 2.0 7.0 2.0 8.5
t
PZH
Enable Time 2.0 7.0 2.0 8.5
ns
t
PZL
DIR to A or B 3.0 9.5 3.0 10.0
t
PHZ
Disable Time 1.5 7.5 1.5 8.5
ns
t
PLZ
DIR to A or B 2.5 8.5 2.5 9.5
’F646B
AC Operating Requirements
74F 54F 74F
Symbol Parameter
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com Units
V
CC
ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 5.0 4.0
ns
t
s
(L) Bus to Clock 5.0 4.0
th(H) Hold Time, HIGH or LOW 1.5 1.5
ns
t
h
(L) Bus to Clock 1.5 1.5
tw(H) Clock Pulse Width 5.0 5.0
ns
t
w
(L) HIGH or LOW 5.0 5.0
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 646/646B/648 S C X
Temperature Range Family Special Variations
74F
e
Commercial QBeMilitary grade device with
54F
e
Military environmental and burn-in
processing
Device Type
X
e
Devices shipped in 13×reel
Package Code
Temperature Range
SP
e
Slim Plastic DIP
C
e
Commercial
SD
e
Slim Ceramic DIP
(0
§
Ctoa70§C)
S
e
Small Outline (SOIC)
M
e
Military
MSA
e
Shrink Small Outline SOIC EIAJ Type II (M646 only)
(
b
55§Ctoa125§C)
L
e
Leadless Chip Carrier
F
e
Flatpak
8
Page 9
Physical Dimensions inches (millimeters)
28-Lead Ceramic Leadless Chip Carrier, Type C
NS Package Number E28A
24-Lead (0.300×Wide) Ceramic Dual-In-Line Package (SD)
NS Package Number J24F
9
Page 10
Physical Dimensions inches (millimeters) (Continued)
24-Lead (0.300×Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M24B
10
Page 11
Physical Dimensions inches (millimeters) (Continued)
24-Lead Molded Shrink Small Outline Package, EIAJ, Type II
NS Package Number MSA24
24-Lead (0.300×Wide) Molded Dual-In-Line Package (SP)
NS Package Number N24C
11
Page 12
54F/74F646
#
74F646B
#
54F/74F648 Octal Transceiver/Register with TRI-STATE Outputs
Physical Dimensions inches (millimeters) (Continued)
24-Lead Cerpack
NS Package Number W24C
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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