Datasheet 5962-8957501XC, 5962-8957501XX Datasheet (UTMC)

RTS-1

UTI760A RTS Remote Terminal for Stores

F

EATURES

❐

Complete MIL-STD-1760A Notice I through III
remote terminal interface

❐

1K x 16 of on-chip static RAM for message data,
completely accessible to host

❐

Self-test capability, including continuous loop-back
compare

❐

Programmable memory mapping via pointers for
efficient use of internal memory, including buffering
multiple messages per subaddress

❐

R T-RT Terminal Address Compare

❐

Command word stored with incoming data for
enhanced data management

❐

User selectable RAM Busy (RBUSY) signal for slow
or fast processor interfacing

❐

Full military operating temperature range, -55°C to
+125

°

C, screened to the specific test methods listed in

T able I of MIL-STD-883, Method 5004, Class B, also
Standard Military Drawing available

❐

Available in 68-pin pingrid array package

I

NTRODUCTION

The UT1760A RTS is a monolithic CMOS VLSI solution
to the requirements of the dual-redundant MIL-STD-1553B
interface as specified by MIL-STD-1760A. Designed to
reduce cost and space in the mission stores interface, the
RTS integrates the remote terminal logic with a user­configured 1K x 16 static RAM. In addition, the RTS has a
flexible subsystem interface to permit use with most
processors or controllers.

The RTS provides all protocol, data handling, error
checking, and memory control functions, as well as
comprehensive self-test capabilities. The RTS’s memory
meets all of a mission store’s message storage needs through
user-defined memory mapping. This memory-mapped
architecture allows multiple message buffering at

DECODER

COMMAND
RECOGNITION

DECODER

ENCODER

MUX

OUT

OUT

IN

IN

MCSA(4:0)

RTA(4:0)
REMOTE TERMINAL
ADDRESS

MODE CODE/
SUBADDRESS

CONTROL AND
ERROR LOGIC

CONTROL
INPUTS

STATUS
OUTPUTS

1K X 16 RAM

ADDR(9:0)

PTR REGISTER

DATA(15:0)

2MHz

12MHz

RESET

CLOCK AND RESET

LOGIC

Figure 1. UT1760A RTS Functional Block Diagram

OUTPUT MULTIPLEXING AND

SELF-TEST WRAP AROUND LOGIC

RTS-2

Table of Contents

1.0 ARCHITECTURE AND OPERATION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1 Memory Map and Host Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 RTS RAM Pointer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 Mode Code and Subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5 MIL-STD-1760A Subaddress and Mode Code Definitions . . . . . . . . . . . . . . . 9

1.6 Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.7 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.8 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.9 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.10 RT-RT Transfer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.0 MEMORY MAP EXAMPLE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.0 PIN IDENTIFICATION AND DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.0 MAXIMUM AND RECOMMENDED OPERATING CONDITIONS

22

5.0 DC ELECTRICAL CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6.0 AC ELECTRICAL CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.0 PACKAGE OUTLINE DRAWING

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

RTS-3

1.0 A

RCHITECTURE AND OPERATION

The UT1760A RTS is an interface device linking a MIL­STD-1553 serial data bus and a host microprocessor system.
The RTS’s MIL-STD-1553B interface includes encoding/
decoding logic, error detection, command recognition, 1K
x 16 of SRAM, pointer registers, clock, and reset circuits.
Illegal subaddress circuitry makes the RTS MIL-STD­1760A-specific.

1.1 Memory Map and Host Memory Interface

The host can access the 1K x 16 RAM memory like a
standard RAM device through the 10-bit address and 16-bit
data buses. The host uses the Chip Select (CS

), Read/Write

(RD/WR

), and Output Enable (OE) signals to control data

transfer to and from memory . When the RTS requires access

to its own internal RAM, it asserts the RBUSY signal to
alert the host. The RBUSY signal is programmable via the
internal Control Register to be asserted either 5.7ms or

2.7ms prior to the RTS needing access to its internal RAM.
The RTS stores MIL-STD-1760A messages in 1K x 16 of

on-chip RAM. For efficient use of the 1K x 16 memory on
the R TS, the host programs a set of pointers to map where
the 1760A message is stored. The RTS uses the upper 64
words (address 3C0 (hex) through 3FF (hex)) as pointers.
The RTS pro vides pointers for all 30 recei ve subaddresses,
all 30 transmit subaddresses, and four mode code
commands with associated data words as defined in
MIL-STD-1553B. The remaining 960 words of memory
contain receive, transmit, and mode code data in a
host-defined structure.

Figure 2. RTS Memory Map

15 MSB 0 LSB

RTS Memory Map

3C0 (hex)

3DF (hex)

3C1 (hex)

3DE (hex)

RCV SUBADDRESS 01

RCV SUBADDRESS 30

XMIT VECTOR WORD MODE CODE (W/DATA)

SYNCHRONIZE MODE CODE (W/DATA)

15 MSB 0 LSB

3FF (hex)

XMIT LAST COMMAND MODE CODE (W/DATA)

XMT BIT WORD MODE CODE (W/DATA)

3E0 (hex)

XMT SUBADDRESS 30

3FE (hex)

3E1 (hex)

15 MSB 0 LSB

000 (hex)

3BF(hex)

Message
Storage
Locations

Receive
Message
Pointers

Transmit
Message
Pointers

(3C1 TO 3DE)

(3E1 TO 3FE)

XMT SUBADDRESS 01

RTS-4

1.2 RTS RAM Pointer Structure

The RAM 16-bit pointers have a 6-bit index field and a
10-bit address field. The 6-bit index field allows for the
storage of up to 64 messages per subaddress. A message
consists of the 1553 command word and its associated
data words.

The 16-bit pointer for Transmit Last Command Mode Code
is located at memory location 3E0 (hex). The T ransmit Last
Command Mode Code pointer buffers up to 63 command
words. An example of command word storage follows:

Example:
3E0 (hex) Contents = FC00 (hex)

11 1111 00 0000 0000
Address Field = 000 (hex)

Index Field = 3F (hex)

First command word storage location (3E0 = F801):

Address Field = 001 (hex)
Index Field = 3E (hex)

Sixty-third command word storage location

(3E0 = 003F):

Address Field = 03F (hex)
Index Field = 00 (hex)

Sixty-fourth command word storage location (3E0 = 003F)
(previous command word overwritten):

Address Field = 03F (hex)
Index Field = 00 (hex)

The Transmit Last Command Mode Code has Address Field
boundary conditions for the location of command word
buffers. The host can allocate a maximum 63 sequential
locations following the Address Field starting address. F or
proper operation, the Address Field must start on an I x 40
(hex) address boundary, where I is greater than or equal to
zero and less than or equal to 14. A list of valid Index and
Address Fields follows:

Figure 3. Message Pointer Structure

MESSAGE INDEX MESSAGE DATA ADDRESS

15 (MSB) 0 (LSB)

Message Index:
Defines the maximum
messages buffered for the
given subaddress.

Message Data Address:
Indicates the starting memory
address for incoming message
storage.

10 9

I Valid Index Fields Valid Address Fields

0 3F (hex) to 00 (hex) 000 (hex) to 03F(hex)
1 3F (hex) to 00 (hex) 040 (hex) to 07F (hex)
2 3F (hex) to 00 (hex) 080 (hex) to 0BF(hex)
3 3F (hex) to 00 (hex) 0C0 (hex) to 0FF (hex)
4 3F (hex) to 00 (hex) 100 (hex) to 13F (hex)
5 3F (hex) to 00 (hex) 140 (hex) to 17F (hex)
6 3F (hex) to 00 (hex) 180 (hex) to 1BF (hex)
7 3F (hex) to 00 (hex) 1C0 (hex) to 1FF (hex)
8 3F (hex) to 00 (hex) 200 (hex) to 23F (hex)
9 3F (hex) to 00 (hex) 240 (hex) to 27F (hex)
10 3F (hex) to 00 (hex) 280 (hex) to 2BF (hex)
11 3F (hex) to 00 (hex) 2C0 (hex) to 2FF (hex)
12 3F (hex) to 00 (hex) 300 (hex) to 33F (hex)
13 3F (hex) to 00 (hex) 340 (hex) to 37F (hex)
14 3F (hex) to 00 (hex) 380 (hex) to 3BF (hex)

RTS-5

1.3 Internal Registers

The RTS uses two internal registers to allow the host to
control the RTS operation and monitor its status. The host
uses the Control (CTRL

) signal along with Chip Select (CS),

Read/Write (RD/WR

), and Output Enable (OE) to read the
16-bit Status Register or write to the 13-bit Control Register .
No address data is needed to select a register. The Control
Register toggles bits in the MIL-STD-1553B status word,

enables the biphase inputs, recognizes broadcast
commands, selects Notice I and II or III, determines RAM
Busy (RBUSY) timing, selects disconnect or terminal active
flag, and puts the part in self-test mode. The Status Register
supplies operational status of the UT1760A RTS to the host.
These registers must be initialized before attempting RTS
operation. Internal registers can be accessed while RBUSY
is active.

Subaddress/Mode Code RAM Location Subaddress/Mode Code RAM Location

Transmit Vector Word Mode Code 3C0 (hex) Transmit Last Command Mode Code 3E0 (hex)
Receive Subaddress 01 3C1 (hex) Transmit Subaddress 01 3E1 (hex)
Receive Subaddress 02 3C2 (hex) Transmit Subaddress 02 3E2 (hex)
Receive Subaddress 03 3C3 (hex) Transmit Subaddress 03 3E3 (hex)
Receive Subaddress 04 3C4 (hex) Transmit Subaddress 04 3E4 (hex)
Receive Subaddress 05 3C5 (hex) Transmit Subaddress 05 3E5 (hex)
Receive Subaddress 06 3C6 (hex) Transmit Subaddress 06 3E6 (hex)
Receive Subaddress 07 3C7 (hex) Transmit Subaddress 07 3E7 (hex)
Receive Subaddress 08 3C8 (hex) Transmit Subaddress 08 3E8 (hex)
Receive Subaddress 09 3C9 (hex) Transmit Subaddress 09 3E9 (hex)
Receive Subaddress 10 3CA (hex) Transmit Subaddress 10 3EA (hex)
Receive Subaddress 11 3CB (hex) Transmit Subaddress 11 3EB (hex)
Receive Subaddress 12 3CC (hex) Transmit Subaddress 12 3EC (hex)
Receive Subaddress 13 3CD (hex) Transmit Subaddress 13 3ED (hex)
Receive Subaddress 14 3CE (hex) Transmit Subaddress 14 3EE (hex)
Receive Subaddress 15 3CF (hex) Transmit Subaddress 15 3EF (hex)
Receive Subaddress 16 3D0 (hex) Transmit Subaddress 16 3F0 (hex)
Receive Subaddress 17 3D1 (hex) Transmit Subaddress 17 3F1 (hex)
Receive Subaddress 18 3D2 (hex) Transmit Subaddress 18 3F2 (hex)
Receive Subaddress 19 3D3 (hex) Transmit Subaddress 19 3F3 (hex)
Receive Subaddress 20 3D4 (hex) Transmit Subaddress 20 3F4 (hex)
Receive Subaddress 21 3D5 (hex) Transmit Subaddress 21 3F5 (hex)
Receive Subaddress 22 3D6 (hex) Transmit Subaddress 22 3F6 (hex)
Receive Subaddress 23 3D7 (hex) Transmit Subaddress 23 3F7 (hex)
Receive Subaddress 24 3D8 (hex) Transmit Subaddress 24 3F8 (hex)
Receive Subaddress 25 3D9 (hex) Transmit Subaddress 25 3F9 (hex)
Receive Subaddress 26 3DA (hex) Transmit Subaddress 26 3FA (hex)
Receive Subaddress 27 3DB (hex) Transmit Subaddress 27 3FB (hex)
Receive Subaddress 28 3DC (hex) Transmit Subaddress 28 3FC (hex)
Receive Subaddress 29 3DD (hex) Transmit Subaddress 29 3FD (hex)
Receive Subaddress 30 3DE (hex) Transmit Subaddress 30 3FE (hex)
Synchronize w/Data Word Mode Code 3DF (hex) Transmit Bit Word Mode Code 3FF (hex)

RTS-6

Control Register (Write Only)

The 13-bit write-only Control Register manages the operation of the RTS. Write to the Control Register by applying a logic
one to OE

, and a logic zero to CTRL, CS, and RD/WR. Data is loaded into the Control Register via I/O pins DATA(12:0).

Control register write must occur 50ns before the rising edge of COMSTR

to latch data into the outgoing status word.

Bit
Number

Initial
Condition

Description

Bit 0 [1] Channel A Enable. A logic 1 enables Channel A biphase inputs.
Bit 1 [1] Channel B Enable. A logic 1 enables Channel B biphase inputs.
Bit 2 [0] Terminal Flag. A logic 1 sets the Terminal Flag bit of the Status Word.
Bit 3 [1] System Busy. A logic 1 sets the Busy bit of the Status Word and limits RTS access to the

memory. No data word can be retrieved or stored; command words will be stored.
Bit 4 [0] Subsystem Busy. A logic 1 sets the Subsystem Flag bit of the Status Word.
Bit 5 [0] Self-Test Channel Select. This bit selects which channel the self-test checks; a logic 1 selects

Channel A and a logic 0 selects Channel B.
Bit 6 [0] Self-Test Enable. A logic 1 places the RTS in the internal self-test mode and inhibits normal

operation. Channels A and B should be disabled if self-test is chosen.
Bit 7 [0] Service Request. A logic 1 sets the Service Request bit of the Status Word.
Bit 8 [0] Instrumentation. A logic 1 sets the Instrumentation bit of the Status Word.
Bit 9 [1] Broadcast Enable. A logic 1 enables the RTS to recognize broadcast commands.
Bit 10 [1] Notice Select. A logic 1 enables Notice III operation; logic 0 enables Notice I or II operation.
Bit 11 [1] DSCNCT/TERA

CT Pin Select. A logic 1 selects the “Disconnect” function; a logic 0 selects

the “Terminal Active” function.
Bit 12 [1] RBUSY Time Select. A logic 1 selects a 5.7µs RBUSY alert; a logic 0 selects a 2.7µs

RBUSY alert.
[] - Values in parentheses indicate the initialized values of these bits.

X X X NO

TICE

PS BCEN INS SRQ ITST SUBS BUSY TF CH BENCH A

EN

ITCSRBUSY

TS

[1]

Figure 4a. Control Register

[1][0][1][0][0][0][0][0][1][1][1][1]

[ ] defines reset state

CONTROL REGISTER (WRITE ONLY):

MSB

LSB

RTS-7

Status Register (Read Only):

The 16-bit read-only Status Register provides the R TS system status. Read the Status Register by applying a logic 0 to CTRL ,
CS

, and OE, and a logic 1 to RD/WR. The 16-bit contents of the Status Register are read from data I/O pins DATA(15:0).

Bit
Number

Initial
Condition

Description

Bit 0 [0] MCSA0. The LSB of the mode code or subaddress as indicated by the logic state of bit 5.
Bit 1 [0] MCSA1. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 2 [0] MCSA2. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 3 [0] MCSA3. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 4 [0] MCSA4. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 5 [0] MC/SA. A logic 1 indicates that bits 4 through 0 are the subaddress of the last command word,

and that the last command word was a normal transmit or receive command. A logic 0 indicates
that bits 4 through 0 are a mode code, and that the last command was a mode command.

Bit 6 [1] Channel A/B

. A logic 1 indicates that the most recent command arri v ed on Channel A; a logic 0

indicates that it arrived on Channel B.

Bit 7 [1] Channel B Enabled. A logic 1 indicates that Channel B is available for both reception and

transmission.

Bit 8 [1] Channel A Enabled. A logic 1 indicates that Channel A is available for both reception and

transmission.

Bit 9 [1] Terminal Flag Enabled. A logic 1 indicates that the Bus Controller has not issued an Inhibit

Terminal Flag Mode Code. A logic 0 indicates that the Bus Controller, via the above mode
code, is overriding the host system’s ability to set the Terminal Flag bit of the status word.

Bit 10 [1] Busy. A logic 1 indicates the Busy bit is set. This bit is reset when the System Busy bit in the

Control Register is reset.

Bit 11 [0] Self-Test. A logic 1 indicates that the chip is in the internal self-test mode. This bit is reset

when the self-test is terminated.

Bit 12 [0] TA Parity Error. A logic 1 indicates the wrong Terminal Address parity; it causes the biphase

inputs to be disabled. TA Parity Error results in the Message Error bit being set to a logic one,
and Channels A and B become disabled.

Bit 13 [0] Message Error. A logic 1 indicates that a message error has occurred since the last Status Reg-

ister read. This bit is not reset until the Status Register has been examined. Message error con­dition must be removed before reading the Status Register to reset the Message Error bit.

Bit 14 [0] Valid Message. A logic 1 indicates that a valid message has been received since the last Status

Register read. This bit is not reset until the Status Register has been examined.

Bit 15 [0] Terminal Active. A logic 1 indicates the device is executing a transmit or receive operation.

Same as TERA

CT output except active high. (Always TERACT; never DSCNCT.)

[] - Values in parentheses indicate the initialized values of these bits.

SELF­TEST

TERM
ACTV

VAL
MESS

MESS
ERR

TAPA
ERR

BUSY TFEN CH AENCH BENCHNL

A/B

MCSA 4MCSA 3MCSA 2MCSA 1MCSA

0

MC/
SA

[0][0][0][0][0][0][1][1][1][1][1][0][0][0][0][0]

[ ] defines reset state

STATUS REGISTER (READ ONLY):

MSB LSB

Figure 4b. Status Register

RTS-8

1.4 Mode Code and Subaddress

The UT1760A RTS provides two modes of illegal
subaddress decoding, one meeting MIL-STD-1760A
Notices I and II, and the other meeting MIL-STD-1760A
Notice III. In addition, the device has automatic internal
illegal command decoding for reserved MIL-STD-1553B
mode codes. These definitions are extracted from MIL­STD-1760A and reviewed in section 1.5 of this document.
Upon command word validation and decode, status pins
MCSA(4:0) and MC

/SA become valid. Status pin MC/SA

will indicate whether the data on pins MCSA(4:0) is mode
code or subaddress information. Status Register bits 0
through 5 contain the same information as pins MCSA(4:0)
and MC

/SA. The system designer can use signals

MCSA(4:0), MC

/SA, BRDCST, RTRT, etc. to illegalize
mode codes, subaddresses, and other message formats
(broadcast and RT-to-RT) via the Illegal Command
(ILLCOM) input to the part.

RTS MODE CODE HANDLING PROCEDURE

T/R Mode Code Function Operation

0 10100 Selected Transmitter Shutdown

2

1. Command word stored

2. MERR pin asserted

3. MERR bit set in Status Register

4. Status word transmitted

0

10101

Override Selected Transmitter
Shutdown

2

1. Command word stored

2. MERR pin asserted

3. MERR bit set in Status Register

4. Status word transmitted

0 10001 Synchronize (w/Data) 1. Command word stored

2. Data word stored

3. Status word transmitted

1 00000 Dynamic Bus Control

2

1. Command word stored

2. MERR pin asserted

3. MERR bit set in Status Register

4. Status word transmitted

1 00001 Synchronize

1

1. Command word stored

2. Status word transmitted

1 00010 Transmit Status Word 3 1. Command word stored

2. Status word transmitted

1 00011 Initiate Self-Test

1

1. Command word stored

2. Status word transmitted

1 00100 Transmitter Shutdown 1. Command word stored

2. Alternate bus shutdown

3. Status word transmitted

1 00101 Override Transmitter Shutdown 1. Command word stored

2. Alternate bus enabled

3. Status word transmitted

1 00110 Inhibit Terminal Flag Bit 1. Command word stored

2. Terminal Flag bit set to zero and disabled

3. Status word transmitted

1 00111 Override Inhibit Terminal Flag 1. Command word stored

2. Terminal Flag bit enabled, but not set to logic one

3. Status word transmitted

1 01000 Reset Remote Terminal

1

1. Command word stored

2. Status word transmitted

1 10010 Transmit Last Command

Word 3

1. Status word transmitted

2. Last command word transmitted

1 10000 Transmit Vector Word 1. Command word stored

2. Status word transmitted

3. Data word transmitted

1 10011 Transmit BIT Word 1. Command word stored

2. Status word transmitted

3. Data word transmitted

Notes:

1. Further host interaction required for mode code operation.

2. Reserved mode code; A) MERR pin asserted, B) MESS ERR bit set, C) status word transmitted (ME bit set to logic one).

3. Status word not affected.

4. Undefined mode codes are treated as reserved mode codes.

RTS-9

1.5 MIL-STD-1760A Subaddress and Mode Code Definitions

Table 1. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice I

Subaddress Field
Binary (Decimal)

Message Format

Description

Receive Transmit

00000 (00) B.40.1.1.3

1

B.40.1.1.3 Mode Code Indicator
00001 (01) Reserved B.40.2.1 2 Store Description
00010 (02) User Defined User Defined
00011 (03) Reserved Reserved
00100 (04) User Defined User Defined
00101 (05) Reserved Reserved
00110 (06) User Defined User Defined
00111 (07) User Defined User Defined
01000 (08) Reserved Reserved
01001 (09) User Defined User Defined
01010 (10) User Defined User Defined
01011 (11) Reserved Reserved
01100 (12) User Defined User Defined
01101 (13) User Defined User Defined
01110 (14) Reserved Reserved
01111 (15) Reserved User Defined
10000 (16) User Defined User Defined
10001 (17) User Defined User Defined
10010 (18) User Defined User Defined
10011 (19) Reserved Reserved Nuclear Weapon
10100 (20) User Defined User Defined
10101 (21) Reserved User Defined
10110 (22) User Defined User Defined
10111 (23) User Defined User Defined
11000 (24) User Defined User Defined
11001 (25) User Defined User Defined
11010 (26) User Defined User Defined
11011 (27) Reserved Reserved Nuclear Weapon
11100 (28) User Defined User Defined
11101 (29) User Defined User Defined
11110 (30) User Defined User Defined
11111 (31) B.40.1.1.3 B.40.1.1.3 Mode Code Indicator

Notes:

1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition.

2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition.

3. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.

RTS-10

Table 2. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice II

Subaddress Field
Binary (Decimal)

Message Format

Description

Receive Transmit

00000 (00) B.40.1.1.3

1

B.40.1.1.3 Mode Code Indicator
00001 (01) Reserved B.40.2.1 2 Store Description
00010 (02) User Defined User Defined
00011 (03) Reserved Reserved
00100 (04) User Defined User Defined
00101 (05) Reserved Reserved
00110 (06) User Defined User Defined
00111 (07) User Defined User Defined
01000 (08) Reserved Reserved
01001 (09) User Defined User Defined
01010 (10) User Defined User Defined
01011 (11) Reserved Reserved
01100 (12) User Defined User Defined
01101 (13) User Defined User Defined
01110 (14) Reserved Reserved
01111 (15) Reserved User Defined
10000 (16) User Defined User Defined
10001 (17) User Defined User Defined
10010 (18) User Defined User Defined
10011 (19) Reserved Reserved Nuclear Weapon
10100 (20) User Defined User Defined
10101 (21) Reserved User Defined
10110 (22) User Defined User Defined
10111 (23) User Defined User Defined
11000 (24) User Defined User Defined
11001 (25) User Defined User Defined
11010 (26) User Defined User Defined
11011 (27) Reserved Reserved Nuclear Weapon
11100 (28) User Defined User Defined
11101 (29) User Defined User Defined
11110 (30) User Defined User Defined
11111 (31) B.40.1.1.3 B.40.1.1.3 Mode Code Indicator

Notes:

1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition.

2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition.

3. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.

RTS-11

Table 3. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice III

Subaddress Field
Binary (Decimal)

Message Format

Description

Receive Transmit

00000 (00) B.40.1.1.3

1

B.40.1.1.3 Mode Code Indicator
00001 (01) Reserved B.40.2.1 2 Store Description
00010 (02) User Defined User Defined
00011 (03) User Defined User Defined
00100 (04) User Defined User Defined
00101 (05) User Defined User Defined
00110 (06) User Defined User Defined
00111 (07) User Defined User Defined
01000 (08) Reserved Reserved Test Only
01001 (09) User Defined User Defined
01010 (10) User Defined User Defined
01011 (11) B.40.2.2.1 3 B.40.2.2.1 Mission Store Control/Monitor
01100 (12) User Defined User Defined
01101 (13) User Defined User Defined
01110 (14) B.40.1.1.5.8 4 B.40.1.5.8 Mass Data Transfer
01111 (15) User Defined User Defined
10000 (16) User Defined User Defined
10001 (17) User Defined User Defined
10010 (18) User Defined User Defined
10011 (19) B.40.2.2.4

5

B.40.2.2.5

6

Nuclear W eapon
10100 (20) User Defined User Defined
10101 (21) User Defined User Defined
10110 (22) User Defined User Defined
10111 (23) User Defined User Defined
11000 (24) User Defined User Defined
11001 (25) User Defined User Defined
11010 (26) User Defined User Defined
11011 (27) B.40.2.2.4 B.40.2.2.5 Nuclear Weapon
11100 (28) User Defined User Defined
11101 (29) User Defined User Defined
11110 (30) User Defined User Defined
11111 (31) B.40.1.1.3 B.40.1.1.3 Mode Code Indicator

Notes:

1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition.

2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition.

3. Refer to section B.40.2.2.1 of the MIL-STD-1760A specification for definition.

4. Refer to section B.40.1.1.5.8 of the MIL-STD-1760A specification for definition.

5. Refer to section B.40.2.2.4 of the MIL-STD-1760A specification for defi nition.

6. Refer to section B.40.2.2.5 of the MIL-STD-1760A specification for definition.

7. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.

RTS-12

1.6 Terminal Address

The Terminal Address of the RTS is programmed via five
input pins: RTA(4:0) and R TPTY. Asserting MRST

latches
the R TS’ s T erminal Address from pins R TA(4:0) and parity
bit R TPTY. The address and parity cannot change until the
next assertion of the MRST

. The parity of the Terminal
Address is odd; input pin RTPTY is set to a logic state to
satisfy this requirement. A logic 1 on Status Register
bit 12 indicates incorrect Terminal Address parity. An
example follows:

RTA(4:0) = 05 (hex) = 00101
RTPTY = 1 (hex) = 1

Sum of 1’s = 3 (odd), Status Register bit 12 = 0

RTA(4:0) = 04 (hex) = 00100
RTPTY = 0 (hex) = 0
Sum of 1’s = 1 (odd), Status Register bit 12 = 0

RTA(4:0) = 04 (hex) = 00100
RTPTY = 1 (hex) = 1
Sum of 1’s = 2 (even), Status Register bit 12 = 1

The RTS checks the T erminal Address and parity on Master
Reset. The state of the DSCNCT signal indicates the mated
status of the store. When all six Terminal Address pins
(R TA(4:0), RTPTY) go to a logic one, the DSCNCT pin is
asserted. T o enable the disconnect function (DSCNCT pin)
bit 11 of the Control Register is set to a logic one. With
broadcast disabled, RTA (4:0) = 11111 operates as a normal
RT address.

1.7 Internal Self-Test

Setting bit 6 of the Control Register to a logic one enables
the internal self-test. Disable Channels A and B at this time
to prevent bus activity during self-test by setting bits 0 and
1 of the Control Register to a logic zero. Normal operation
is inhibited when internal self-test is enabled. The self-test
capability of the RTS is based on the f act that the MIL-STD­1553B status word sync pulse is identical to the command
word sync pulse. Thus, if the status word from the encoder
is fed back to the decoder, the RTS will recognize the
incoming status word as a command word and thus cause
the RTS to transmit another status word. After the host
inv okes self-test, the RTS self-test logic forces a status word
transmission even though the RTS has not received a valid
command. The status word is sent to decoder A or B
depending on the channel the host selected for self-test. The
self-test is controlled by the host periodically changing the
bit patterns in the status word being transmitted. Writing to
the Control Register bits 2, 3, 4, 7, 8, and 10 changes the
status word. Monitor the self-test by sampling either the
Status Register or the external status pins (i.e., Command
Strobe (COMSTR

), Transmit/Recei ve (T/R)). For more
detailed explanation of internal self-test, consult UTMC
publication

RTR/RTS Internal Self-Test Routine.

1.8 Power-up and Master Reset

After power-up, reset initializes the part with its biphase
ports enabled, latches the T erminal Address, selects Notice
III subaddress decoding, and turns on the busy option. The
device is ready to accept commands from the MIL-STD­1553B bus. The busy flag is asserted while the host is loading
the message pointers and messages. After this task is
completed, the host removes the busy condition via a
Control Register write to the RTS. On power-up if the
terminal address parity (odd) is incorrect, the biphase inputs
are disabled and the message error pin (MERR) is asserted.
This condition can also be monitored via bit 12 of the Status
Register. The MERR pin is negated on reception of first
valid command.

1.9 Encoder and Decoder

The RTS interf aces directly to a bus transmitter/ receiver via
the RTS Manchester II encoder/decoder. The UT1760A
RTS receives the command word from the MIL-STD­1553B bus and processes it either by the primary or
secondary decoder. Each decoder checks for the proper sync
pulse and Manchester waveform, edge ske w, correct number
of bits, and parity. If the command is a receive command,
the RTS processes each incoming data word for correct
format and checks the control logic for correct word count
and contiguous data. If an inv alid message error is detected,
the message error pin is asserted, the RTS ceases processing
the remainder (if any) of the message, and it then suppresses
status word transmission. Upon command validation
recognition, the external status outputs are enabled.
Reception of illegal commands does not suppress status
word transmission.

The RTS automatically compares the transmitted word
(encoder word) to the reflected decoder word by way of the
continuous loop-back feature. If the encoder word and
reflected word do not match, the transmitter error pin
(TXERR) is asserted. In addition to the loop-back compare
test, a timer precludes a transmission greater than 760µs by
the assertion of Fail-safe T imer (TIMER

ON). This timer is
reset upon receipt of another command. (RT-to-R T transfer
time-out = 57µs).

1.10 RT-RT Transfer Compare

The RT-to-R T T erminal Address compare logic makes sure
that the incoming status word’ s Terminal Address matches
the T erminal Address of the transmitting RT specified in the
command word. An incorrect match results in setting the
message error bit and suppressing transmission of the
status word.

RTS-13

1.11 Illegal Command Decoding

The host has the option of asserting the ILLCOM pin to
illegalize a received command w ord. On receipt of an illegal
command, the RTS sets the Message Error bit in the status
word, sets the message error output, and sets the message
error latch in the Status Register.

The following RTS outputs may be used to externally
decode an illegal command, Mode Code or Subaddress
indicator (MC

/SA), Mode Code or Subaddress bus

MCSA(4:0), Command Strobe (COMSTR

), Broadcast

(BRDCST

), and Remote Terminal to Remote Terminal

transfer (RTRT) (see figure 21 on page 34.)
To illegalize a transmit command, the ILLCOM pin must

be asserted within 3.3µs after VALMSG goes to a logic 1 if
the RTS is to respond with the Message Error bit of the status
word at a logic 1. If the illegal command is mode code 2, 4,
5, 6, 7, or 18, the ILLCOM pin must be asserted within 664ns
after Command Strobe (COMSTR

) transitions to logic 0.
Asserting the ILLCOM pin within the 664ns inhibits the
mode code function. For mode code illegalization, assert the
ILLCOM pin until the VALMSG signal is asserted.

For an illegal receiv e command, the ILLCOM pin must be
asserted within 18.2µs after the COMSTR

transitions to a
logic 0 in order to suppress data words from being stored.
In addition, the ILLCOM pin must be at a logic 1 throughout
the reception of the message until VALMSG is asserted.
This does not apply to illegal transmit commands since the
status word is transmitted first.

The above timing conditions also apply when the host
externally decodes an illegal broadcast command. The host
must remove the illegal command condition so that the next
command is not falsely decoded as illegal.

2.0 M

EMORY MAP EXAMPLE

Figures 5 and 6 illustrate the UT1760A RTS b uffering three
receive command messages to Subaddress 4. The receive
message pointer for Subaddress 4 is located at 03C4 (hex)
in the 1K x 16 RAM. The 16-bit contents of location 03C4
(hex) point to the memory location where the first receive
message is stored. The Address Field defined as bits 0
through 9 of address 03C4 (hex) contain address
information. The Index Field defined as bits 10 through 15
of address 03C4 (hex) contain the message buffer inde x (i.e.,
number of messages buffered).

Figure 5 demonstrates the updating of the message pointer
as each message is received and stored. The memory storage
of these three messages is shown in figure 6. After receiving
the third message for Subaddress 4 (i.e., Index Field equals
zero) the Address Field of the message pointer is not
incremented. If the host does not update the receive
message pointer for Subaddress 4 before the next receive
command for Subaddress 4 is accepted, the third message
will be overwritten.

Figures 7 and 8 show an example of multiple message
retrieval from Subaddress 16 upon reception of a MIL-STD­1553B transmit command. The message pointer for transmit
Subaddress 16 is located at 03F0 (hex) in the 1K x 16 RAM.
The 16-bit contents of location 03F0 (hex) point to the
memory location where the first message data words
are stored.

Figure 7 demonstrates the updating of the message pointer
as each message is received and stored. The data memory
for these three messages is shown in figure 8.

RTS-14

MIL-STD-1553 Bus Activity:

Figure 5. RTS Message Handling

Receive Subaddress 4;
data pointer at 03C4
(hex). (Initial condition)

0840 (hex)

03C4 (hex)

INDEX = 0000 10
ADDRESS = 00 0100 0000

0445 (hex)

03C4 (hex)

INDEX = 0000 01
ADDRESS = 00 0100 0101

After message #1,
4 data words plus
command word.

0048 (hex)

03C4 (hex)

INDEX = 0000 00
ADDRESS = 00 0100 1000

After message #2,
2 data words plus
command word.

0048 (hex)

03C4 (hex)

INDEX = 0000 00
ADDRESS = 00 0100 1000

After message #3,
4 data words plus
command word.

Example:
Remote terminal will receive and buffer three MIL-STD-1553 receive commands
of various word lengths to Subaddress 4.

CMD WORD #1 DW1 DW2 DW3DW0

CMD WORD #2 DW1DW0

CMD WORD #3 DW1 DW3DW0

SA = 4

SA = 4

SA = 4

T/R

= 0

T/R

= 0

T/R

= 0

WC = 4

WC = 2

WC = 4

DW2

040 (hex)
041 (hex)
042 (hex)
043 (hex)
044 (hex)
045 (hex)
046 (hex)
047 (hex)
048 (hex)
049 (hex)
04A (hex)
04B (hex)
04C (hex)

Figure 6. Memory Storage Subaddress 4

COMMAND WORD #2

DATA WORD 0
DATA WORD 1

DATA WORD 2
DATA WORD 3

COMMAND WORD #1

DATA WORD 1

COMMAND WORD #3

DATA WORD 0
DATA WORD 1
DATA WORD 2
DATA WORD 3

DATA WORD 0

0840 (hex)

03C4 (hex)

0445 (hex)

03C4 (hex)

0048 (hex)

03C4 (hex)

0048 (hex)

03C4 (hex)

RTS-15

Figure 7. RTS Message Handling

0830 (hex) INDEX = 0000 10

ADDRESS = 00 0011 0000

0434 (hex)

03F0 (hex)

INDEX = 0000 01
ADDRESS = 00 0011 0100

After message #1,
4 data words.

0036 (hex)03F0 (hex)

INDEX = 0000 00
ADDRESS = 00 0011 0110

After message #2,
2 data words.

0036 (hex)03F0 (hex)

INDEX = 0000 00
ADDRESS = 00 0011 0110

After message #3,
4 data words.

Example:
Remote terminal will transmit and buffer three MIL-STD-1553 transmit commands
of various word lengths to Subaddress 16.

CMD WORD #1

DW1

SW

CMD WORD #2

DW1

CMD WORD #3

DW1 DW2 DW3DW0

MIL-STD-1553 Bus Activity:

SA = 16
T/R

= 1

SA = 16
T/R = 1
WC = 4

SA = 16
T/R = 1
WC = 2

WC = 4

Transmit Subaddress 16;
data pointer at 03F0
(hex). (Initial condition)

03F0 (hex)

DW0

SW

SW

DW3

DW2

SW0

030 (hex)
031 (hex)
032 (hex)
033 (hex)

034 (hex)

035 (hex)
036 (hex)
037 (hex)
038 (hex)
039 (hex)

Figure 8. Memory Storage Subaddress 16

DATA WORD 0
DATA WORD 1

DATA WORD 2
DATA WORD 3

DATA WORD 1

DATA WORD 0
DATA WORD 1
DATA WORD 2
DATA WORD 3

DATA WORD 0

0830 (hex)

03F0(hex)

0434 (hex)

03F0 (hex)

0036 (hex)

0

3F0 (hex)

0036 (hex)

3F0 (hex)

034 (hex)

ote:

xample is valid only if message structure is known in advance.

RTS-16

3.0 PIN I

DENTIFICATION AND DESCRIPTION

VDD
V

DD

V

SS

V

SS

MRST

BIPHASE OUT TAZ

TAO
TBZ

TBO

BIPHASE IN

RAZ
RAO

RBZ
RBO

TERMINAL
ADDRESS

RT A0
RT A1
RT A2
RT A3
RT A4

RTPTY

MODE/CODE
SUBADDRESS

MCSA0
MCSA1
MCSA2
MCSA3
MCSA4

STATUS
SIGNALS

MERR

DSCNCT/TERA

CT

TXERR

TIMER

ON

COMSTR

MC/SA

BRDCST

T/R

RTRT

VALMSG

RBUSY

CS

RD/WR

CTRL

OE

ILLCOM

CONTROL
SIGNALS

ADDR9

ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8

ADDRESS
BUS
ADDR(9:0)

DATA12
DATA13
DATA14
DATA15

DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11

DATA BUS
DATA(15:0)

12MHZ
2MHZ

CLOCK

Figure 9. UT1760A RTS Pin Description

UT1760A

RTS

GROUND

RESET

A10
B10

A9
B9

L7
K8

L6
K7

L5
K5

K4

L4

L3
K6

B2
A2
A3
B3
A4

A5
A6
B5
B6
B8
B1
A7
B4
B7
L8
C2

K2
K1
J1
L9
K9

L2
A8

K3

F10

E1

F2

G11

E10
E11
D10
D11
C10
C11
B11

F11

G10

L10

K10

K11

J10

J11

H10
H11

J2

H1
H2
G1
G2
F1
E2

D1
D2

C1

POWER

RTS-17

Legend for TYPE and ACTIVE Fields:

TI = TTL input
TUI = TTL input (pull-up)
TDI = TTL input (pull-down)
TO = TTL output

TTO = Three-state TTL output
TTB = Three-state TTL bidirectional
AL = Active low
AH = Active high
[] - Value in parentheses indicates initial state of

these pins.

DATA BUS

ADDRESS BUS

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

DATA15

B11 TTB -- Bit 15 (MSB) of the bidirectional Data bus.
DATA14 C11 TTB -- Bit 14 of the bidirectional Data bus.
DATA13 C10 TTB -- Bit 13 of the bidirectional Data bus.
DATA12 D11 TTB -- Bit 12 of the bidirectional Data bus.
DATA11 D10 TTB -- Bit 11 of the bidirectional Data bus.
DATA10 E11 TTB -- Bit 10 of the bidirectional Data bus.
DA T A9 E10 TTB -- Bit 9 of the bidirectional Data bus.
DA T A8 F11 TTB -- Bit 8 of the bidirectional Data bus.
DA T A7 G10 TTB -- Bit 7 of the bidirectional Data bus.
DA T A6 H11 TTB -- Bit 6 of the bidirectional Data bus.
DA T A5 H10 TTB -- Bit 5 of the bidirectional Data bus.
DA T A4 J11 TTB -- Bit 4 of the bidirectional Data bus.
DA T A3 J10 TTB -- Bit 3 of the bidirectional Data bus.
DA T A2 K11 TTB -- Bit 2 of the bidirectional Data bus.
DA T A1 K10 TTB -- Bit 1 of the bidirectional Data bus.
DA T A0 L10 TTB -- Bit 0 (LSB) of the bidirectional Data bus.

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

ADDR9 C1 TI -- Bit 9 (MSB) of the Address bus.
ADDR8 D2 TI -- Bit 8 of the Address bus.
ADDR7 D1 TI -- Bit 7 of the Address bus.
ADDR6 E2 TI -- Bit 6 of the Address bus.
ADDR5 F1 TI -- Bit 5 of the Address bus.
ADDR4 G2 TI -- Bit 4 of the Address bus.
ADDR3 G1 TI -- Bit 3 of the Address bus.
ADDR2 H2 TI -- Bit 2 of the Address bus.
ADDR1 H1 TI -- Bit 1 of the Address bus.
ADDR0 J2 TI -- Bit 0 (LSB) of the Address bus.

RTS-18

CONTROL INPUTS

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

CS

K2 TI AL Chip Select. The host processor uses the CS signal for

RTS Status Register reads, Control Register writes, or
host access to the RTS internal RAM.

RD/WR K1 TI -- Read/Write. The host processor uses a high level on this

input in conjunction with CS to read the RTS Status
Register or the RTS internal RAM. A low level on this
input is used in conjunction with CS to write to the RTS
Control Register or the RTS internal RAM.

CTRL J1 TI AL Control. The host processor uses the active low CTRL

input signal in conjunction with CS and
RD/WR to access the RTS registers. A high level on this
input means access is to RTS internal RAM only.

OE L9 TI AL Output Enable. The active low OE signal is used to

control the direction of data flow from the RTS.
For OE = 1, the RTS Data bus is three-state; for
OE = 0, the RTS Data bus is active.

ILLCOM K9 TDI AH Illegal Command. The host processor uses the

ILLCOM input to inform the RTS that the present
command is illegal.

RTS-19

STATUS OUTPUTS

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

MERR
[0]

A5 TO AH Message Error. The active high MERR output signals that

the Message Error bit in the Status Register has been set
due to receipt of an illegal command, or an error during
message sequence. MERR will reset to logic zero on the
receipt of the next valid command.

TXERR
[0]

B5 TO AH Transmission Error. The active high TXERR output is

asserted when the RTS detects an error in the reflected
word versus the transmitted word, using the continuous
loop-back compare feature. Reset on next COMSTR
assertion.

TIMERON
[1]

B6 TO AL Fail-safe Timer. The TIMERON output pulses low for

760µs when the RTS begins transmitting (i.e., rising edge
of VALMSG) to provide a fail-safe timer meeting the
requirements of MIL-STD-1553B. This pulse is reset
when COMSTR goes low or during a Master Reset.

COMSTR
[1]

B8 TO AL Command Strobe. COMSTR is an active low output of

500ns duration identifying receipt of a valid command.

BRDCST
[1]

A7 TO AL Broadcast. BRDCST is an active low output that identifies

receipt of a valid broadcast command.

RTRT
[0]

B7 TO AH Remote Terminal to Remote Terminal. RTRT is an active

high output indicating that the RTS is processing a remote
terminal to remote terminal command.

DSCNCT or
TERA

CT

[X]

A6 TO -- Disconnect or Terminal Active. Bit 11 of the Control

Register selects the mode of this dual-function pin. In the
“Disconnect” mode (bit 11 = 1), the active high DSCNCT
output is asserted when all six Terminal Address pins
(RTA0 - RTA4, RTPTY) go high, indicating a disconnect
condition. In the “Terminal Active” mode (bit 11 = 0), the
active low TERA

CT output is asserted at the beginning of
the RTS access to internal RAM for a given command and
negated after the last access for that command.

VALMSG
[0]

L8 TO AH Valid Message. VALMSG is an active high output

indicating a valid message (including Broadcast) has
been received. VALMSG goes high prior to transmitting
the 1553 status word and is reset upon receipt of the
next command.

RBUSY
[0]

C2 TO AH RTS Busy. RBUSY is asserted high while the RTS is

accessing its own internal RAM either to read or update
the pointers or to store or retrieve data words. RBUSY
becomes active either 2.7µs or 5.7µs before RTS requires
RAM access. This timing is controlled by Control Register
bit 12 (see section 1.3).

T/R
[0]

B4 TO -- Transmit/Receive. A high level on this pin indicates a

transmit command message transfer is being or was
processed, while a low level indicates a receive command
message transfer is being or was processed.

RTS-20

MODE CODE/SUBADDRESS OUTPUTS

REMOTE TERMINAL ADDRESS INPUTS

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

MC

/SA

[0]

B1 TO -- Mode Code/Subaddress Indicator. If MC/SA is low, it indi-

cates that the most recent command word is a mode code
command. If MC/SA is high, it indicates that the most
recent command word is for a subaddress. This output
indicates whether the mode code/subaddress ouputs (i.e.,
MCSA(4:0)) contain mode code or subaddress information.

MCSA0
[0]

B2 TO -- Mode Code/Subaddress Output 0. If MC/SA is low, this pin

represents the least significant bit of the most recent
command word (the LSB of the mode code). If MC/SA is
high, this pin represents the LSB of the subaddress.

MCSA1
[0]

A2 TO -- Mode Code/Subaddress Output 1.

MCSA2
[0]

A3 TO -- Mode Code/Subaddress Output 2.

MCSA3
[0]

B3 TO -- Mode Code/Subaddress Output 3.

MCSA4
[0]

A4 TO -- Mode Code/Subaddress Output 4. If MC/SA is low, this pin

represents the most significant bit of the mode code. If MC/
SA is high, this pin represents the MSB of the subaddress.

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

RTA4

L3 TUI -- Remote Terminal Address bit 4 (MSB).
RTA3 K4 TUI -- Remote Terminal Address bit 3.
RTA2 L4 TUI -- Remote Terminal Address bit 2.
RTA1 K5 TUI -- Remote Terminal Address bit 1.
RTA0 L5 TUI -- Remote Terminal Address bit 0 (LSB).
RTPTY K6 TUI -- Remote Terminal Address Parity. This input must provide

odd parity for the Remote Terminal Address.

RTS-21

BIPHASE INPUTS

1

Note

:

1. For uniphase operation, tie RAZ (or RBZ) to V

DD

and apply true uniphase input signal to RAO (or RBO).

BIPHASE OUTPUTS

MASTER RESET AND CLOCK

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

RAZ

L7 TI -- Receiver - Channel A, Zero Input. Idle low Manchester

input form the 1553 bus receiver.

RAO K8 TI -- Receiver - Channel A, One Input. This input is the

complement of RAZ.

RBZ L6 TI -- Receiver - Channel B, Zero Input. Idle low Manchester

input from the 1553 bus receiver.

RBO K7 TI -- Receiver - Channel B, One Input. This input is the

complement of RBZ.

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

TAZ
[0]

A10 TO -- Transmitter - Channel A, Zero Output. This Manchester

encoded data output is connected to the 1553 bus
transmitter input. The output is idle low.

TAO
[0]

B10 TO -- Transmitter - Channel A, One Output. This output is the

complement of TAZ. The output is idle low.

TBZ
[0]

A9 TO -- Transmitter - Channel B, Zero Output. This Manchester

encoded data output is connected to the 1553 bus
transmitter input. The output is idle low.

TBO
[0]

B9 TO -- Transmitter - Channel B, One Output. This output is the

complement of TBZ. The output is idle low.

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

MRST

K3 TUI AL Master Reset. Initializes all internal functions of the RTS.

MRST must be asserted 500ns before normal RTS
operation (500ns minimum). Does not reset RAM.

12MHz L2 TI -- 12 MHz Input Clock. This is the RTS system clock that

requires an accuracy greater than 0.01% with a duty cycle
of 50% ± 10%.

2MHz A8 TO -- 2MHz Clock Output. This is a 2MHz clock output

generated by the 12MHz input clock. This clock is
stopped when MRST is low.

RTS-22

POWER AND GROUND

4.0 O

PERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS*

(referenced to VSS)

RECOMMENDED OPERATING CONDITIONS

NAME PIN NUMBER

(PGA)

TYPE ACTIVE DESCRIPTION

V

DD

F10

E1

PWR
PWR

--

--

+5 V

DC

Power. Power supply must be +5 VDC

±

10%.

V

SS

F2

G11

GND
GND

--

--

Reference ground. Zero V

DC

logic ground.

SYMBOL PARAMETER LIMITS UNIT

VDD

DC supply voltage -0.3 to +7.0 V
VIO Voltage on any pin -0.3 to VDD+0.3 V
I

I

DC input current ±10 mA
T

STG

Storage temperature -65 to +150 °C

P

D

Maximum power dissipation

1

300 mW

T

J

Maximum junction temperature +175 °C

Θ

JC

Thermal resistance, junction-to-case 20 °C/W

Note:

1. Does not reflect the added P

D

due to an output short-circuited.

* Stresses outside the listed absolute maximum ratings may cause permanent damage to the de vice. This is a stress rating only,

and functional operation of the device at these or any other conditions beyond limits indicated in the operational
sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect de vice reliability.

SYMBOL PARAMETER LIMITS UNIT

VDD DC supply voltage 4.5 to 5.5 V
V

IN

DC input voltage 0 to V

DD

V
TC Temperature range -55 to +125 °C
F

O

Operating frequency 12 ±.01% MHz

RTS-23

5.0 DC ELECTRICAL CHARACTERISTICS

VDD = 5.0V ± 10%; -55°C < TC <+125°C)

SYMBOL PARAMETER CONDITION MINIMUM MAXIMUM UNIT

V

IL

Low-level input voltage 0.8 V

V

IH

High-level input voltage 2.0 V

I

IN

Input leakage current
TTL inputs
Inputs with pull-down resistors
Inputs with pull-up resistors

VIN = VDD or VSS
V

IN

= VDD

V

IN

= V

SS

-1
110

-2000

1

2000

-110

µA
µA
µA

V

OL

Low-level output voltage IOL = 3.2µA 0.4 V

V

OH

High-level output voltage IOH = -400µA 2.4 V

I

OZ

Three-state output
leakage current

VO = VDD or VSS -10 +10 µA

I

OS

Short-circuit output current

1, 2

VDD = 5.5V, VO = V

DD

VDD = 5.5V, VO = 0V

-90

90 mA

mA

C

IN

Input capacitance 3 ƒ = 1MHz @ 0V 10 pF

C

OUT

Output capacitance 3 ƒ = 1MHz @ 0V 15 pF

C

IO

Bidirect I/O capacitance 3 ƒ = 1MHz @ 0V 20 pF

I

DD

Average operating current

1, 4

ƒ = 12MHz, CL = 50pF 50 mA

QI

DD

Quiescent current Note 5 1.5 mA

Notes:

1. Supplied as a design limit but not guaranteed or tested.

2. Not more than one output may be shorted at a time for a maximum duration of one second.

3. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.

4. Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching.
Voltage supply should be adequately sized and decoupled to handle a lar ge sur ge current.

5. All inputs with internal pull-ups or pull-do wns should be left open circuit. All other inputs tied high or low.

SYNC

BIT TIMES

COMMAND
WORD

5

5 5 1

DATA WORD

1

ST A TUS WORD

SYNC

SYNC

5

1

REMOTE TERMINAL

ADDRESS

SUBADDRESS/MODE

CODE

T/R

DA T A W ORD COUNT/

MODE CODE

P

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

P

DATA

1

1

1 1 1 1

1

Figure 10. MIL-STD-1553B Word Formats

16

REMOTE TERMINAL

ADDRESS

MESSAGE ERROR

INSTRUMENTATION

SERVICE REQUEST

RESERVED

BROADCAST COMMAND RECEIVED

BUSY

SUBSYSTEM FLAG

DYNAMIC BUS CONTROL ACCEPTANCE

TERMINAL FLAG

PARITY

1

1

RTS-24

6.0 AC ELECTRICAL CHARACTERISTICS

(Over recommended operating conditions)

to data valid

to high Z

to response

to response

to response

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

to high Z

to data valid

to responseINPUT

PARAMETERSYMBOL

BUS

INPUT

Notes:

1. Timing measurements made at (V

IH

MIN + VIL MAX)/2.

2. Timing measurements made at (V

OL

MAX + VOH MIN)/2.

3. Based on 50pf load.

4. Unless otherwise noted, all AC electrical characteristics are guaranteed by design or characterization.

1

1

2

2

2

2

V

IH

MIN

V

IL

MAX

V

IH

MIN

V

IL

MAX

V

OH

MIN

V

OL

MAX

V

OH

MIN

V

OL

MAX

V

OH

MIN

V

OL

MAX

t

a

t

b

t

c

t

d

t

e

t

f

t

g

t

h

↑

↑

↑

↑

↑

↑

↓

↓↓

↓
↓
↓

t

a

t

b

t

c

t

d

t

e

t

f

t

g

t

h

IN-PHASE
OUTPUT

OUT-OF-PHASE
OUTPUT

Figure 11a. T ypical Timing Measurements

90%

Figure 11b. AC Test Loads and Input Waveforms

Note:

50pF including scope probe and test socket

Input Pulses

10%10%

90%

< 2ns < 2ns

50pF

3V

0V

5V

D

I

REF

(source)

I

REF

(sink)

V

REF

RTS-25

SYMBOL PARAMETER MIN MAX UNITS

t

12a

CTRL↑ set up wrt CS↓

1

10 -- ns

t

12b

RD/WR ↑ set up wrt CS↓

10 -- ns

t

12c

ADDR(9:0) Valid to CS↓ (Address Set up)

10 -- ns

t

12d

CS↓ to DATA(15:0) Valid

-- 155 ns

t

12e

OE↓ to DATA(15:0) Don’t Care (Active)

-- 65 ns

t

12f

CS↑ to CTRL Don’t Care

0 -- ns

t

12g

CS↑ to ADDR(9:0) Don’t Care

0 -- ns

t

12h

OE↑ to DATA(15:0) High Impedance

-- 40 ns

t

12i

CS↓ to CS↑ 2

220 5500 ns

t

12j

CS↑ to CS↓

85 -- ns

t

12k

CS↑ to RD/WR Don’t Care

0 -- ns

t

12l

CS↑ to DATA(15:0) Invalid 3

25 -- ns

t

12m

OE↓ to OE↑

65 -- ns

Notes:

1. “wrt” defined as “with respect to.”

2. The maximum amount of time that CS

can be held low is 5500ns if the user has selected the 5.7 µs RBUSY option. For the 2.7 µs

RBUSY option, the maximum CS

low time is 2500ns.

3. Assumes OE

is asserted.

12MHz

RD/WR

CS

ADDR(9:0)

OE

DA T A V ALID

DA T A(15:0)

Figure 12. Microprocessor RAM Read

t

12i

t

12a

t

12b

t

12c

t

12d

t

12e

t

12m

t

1h

t

12l

t

12g

t

12k

t

12f

t

12j

CTRL

RTS-26

SYMBOL PARAMETER MIN MAX UNITS

t

13a

CTRL↑ set up wrt CS↓

10 -- ns

t

13b

RD/WR ↑ set up wrt CS↓

10 -- ns

t

13c

ADDR(9:0) Valid to CS↓ (Address set up)

10 -- ns

t

13d

CS↓ to DATA(15:0) Valid CS↓(DATA set up)

0 -- ns

t

13e

OE↓ to DATA(15:0) High Impedance

40 -- ns

t

13f

CS↑ to RD/WR Don’t Care

0 -- ns

t

13g

CS↑ to ADDR(9:0) Don’t Care

0 -- ns

t

13h

CS↑ to DATA(15:0) Don’t Care (Hold-time)

20 -- ns

t

13i

CS↓ to CS↑ 1

180 5500 ns

t

13j

CS↑ to CS↓

85 -- ns

t

13k

CS↑ to CTRL Don’t Care

0 -- ns

Note:

1. The maximum amount of time that CS

can be held low is 5500ns if the user has selected the 5.7 µs RBUSY option. For the 2.7 µs

RBUSY option, the maximum CS

low time is 2500ns.

DATA(15:0)

12MHz

CTRL

RD/WR

CS

ADDR(9:0)

OE

Figure 13. Microprocessor RAM Write

VALID DATA

t

13i

t

13a

t

13b

t

13c

t

13d

t

13e

t

13h

t

13g

t

13f

t

13k

t

13j

RTS-27

SYMBOL PARAMETER MIN MAX UNITS

t

14a

CTRL↓ set up wrt CS↓

0 -- ns

t

14b

RD/WR ↓ set up wrt CS↓

0 -- ns

t

14c

CS↓ to CS↑ 1

50 5500 ns

t

14d

CS↑ to DATA(15:0) Don’t Care (Hold-time)

0 -- ns

t

14e

CS↑ to CTRL Don’t Care

0 -- ns

t

14f

CS↑ to RD/WR Don’t Care

0 -- ns

t

14g

OE↑ to Data(15:0) High Impedance

40 -- ns

t

14h

DATA (15:0) Valid to CS↓ (DATA set up)

0 -- ns

Note:

1. The maximum amount of time that CS

can be held low is 5500ns if the user has selected the 5.7 µs RBUSY option. For the 2.7 µs

RBUSY option, the maximum CS

low time is 2500ns.

12MHz

CTRL

RD/WR

CS

OE

DATA(15:0)

Figure 14. Control Register Write

VALID DATA

t

14c

t

14a

t

14b

t

14h

t

14g

t

14d

t

14f

t

14e

RTS-28

SYMBOL PARAMETER MIN MAX UNITS

t

15a

CTRL↓ set up wrt CS↓

0 -- ns

t

15b

CS↓ to CS↑1

65 5500 ns

t

15c

RD/WR↑ set up wrt CS↓

0 -- ns

t

15d

CS↓ to DATA(15:0) Valid

-- 65 ns

t

15e

CS↑ to CTRL Don’t Care

5 -- ns

t

15f

CS↑ to RD/WR Don’t Care

5 -- ns

t

15g

OE↓ to DATA(15:0) Don’t Care (Active)

-- 65 ns

t

15h

OE↑ to DATA(15:0) High Impedance

-- 40 ns

t

15i

OE↓ to OE↑

65 -- ns

t

15j

CS↓ to DATA(15:0) Don’t Care (Active)

25 -- ns

Note:

1. The maximum amount of time that CS

can be held low is 5500ns if the user has selected the 5.7 µs RBUSY option. For the 2.7µs RBUSY

option, the maximum CS

low time is 2500ns.

12MHz

CTRL

CS

OE

DATA(15:0)

Figure 15. Status Register Read

VALID DATA

t

15b

RD/WR

t

15a

t

15c

t

15d

t

15g

t

15i

t

15h

t

15j

t

15f

t

15e

RTS-29

SYMBOL PARAMETER MIN MAX UNITS

t

16a

VALMSG↑ before TIMERON↓

0 35 ns

t

16b

TIMERON↓ before first BIPHASE OUT O↑

1.2 -- µs

t

16c

TIMERON low pulse width (time-out)

727.3 727.4 µs

t

16d

COMSTR↓ to TIMERON↑

-- 25 ns

t

16e

VALMSG↑ to ILLCOM↑

-- 3.3 µs

t

16f

COMSTR↓ to ILLCOM↑

1

-- 664 ns

t

16f

COMSTR↓ to ILLCOM↑

2

-- 18.2 µs

t

16g

ILLCOM↑ to ILLCOM↓

3

500 -- ns

Notes:

1. Mode code 2, 4, 5, 6, 7, or 18 receiv ed.

2. T o suppress data word storage.

3. For transmit command illeg alization.

A/B
BIPHASE
OUTPUT ZERO

VALMSG

TIMERON

Figure 16. RT Fail-Safe Timer Signal Relationships

t

16a

COMSTR

ILLCOM

t

16c

t

16b

t

16e

t

16g

t

16d

t

16f

RTS-30

SYMBOL PARAMETER MIN MAX UNITS

t

17a

4

12Mhz↑ to MC/SA Valid

0 14 ns

t

17b

Command Word to MC/SA V alid

3

2.1 2.8 µs

t

17c

4

12MHz↑ to COMSTR↓

0 17 ns

t

17d

Command Word to COMSTR↓

3

3.2 3.7 µs

t

17e

4

12MHz↑ to BRDCST↓

0 32 ns

t

17f

Command Word to BRDCST↓

3

2.6 3.2 µs

t

17g

4

12MHz↑ to T/R Valid

0 57 ns

t

17h

Command Wor d toT/R Valid

3

2.2 2.7 µs

t

17i

4

12MHz↑ to VALMSG↑

0 32 ns

t

17j

Command Wor d toV ALMSG↑

1,2,3

6.2 6.7 µs

t

17k

4

12MHz↑ to MERR↑

0 37 ns

t

17l

COMSTR↓ TO COMSTR↑

485 500 ns

Notes:

1. Receive last data word to V alid Message active (VALMSG

↑).

2. Transmit command word to V alid Message active (VALMSG

↑).

3. Command word measured from mid-bit crossing.

4. Guaranteed by test.

12MHz

BIPHASE IN

CS COMMAND WORD P

MC/SA
and MCSA(4:0)

t

17a

COMSTR

BRDCST

T/R

MERR

VALMSG

Figure 17. Status Output Timing

1

Note:

1. Measured from the mid-bit parity crossing.

t

17b

t

17c

t

17d

t

17e

t

17f

t

17g

t

17h

t

17i

t

17j

t

17k

t

17l

RTS-31

SYMBOL PARAMETER MIN MAX UNITS

t

18a

12MHz↑ to RBUSY↑

-- 37 ns

t

18b

Command Wor d toRBUSY↑ 3

3.2 3.8 µs

t

18c

2

12MHz↑ to TERACT↓

0 37 ns

t

18d

Command Wor d to TERACT↓

1,3

3.1 3.7 µs

t

18e

2 12MHz↑ to RTRT↑

0 32 ns

t

18f

Command Word to RTRT↑

3

21.0 22 µs

t

18g

MRST↓ to MRST↑

500 -- ns

t

18h

RBUSY↑ to RBUSY↓ (2.7µs)

(5.7µs)

--

--

5.5

8.5

µs
µs

t

18i

RBUSY↓ to RBUSY↑ (2.7µs)

(5.7µs)

3.10
240

--

--

µs
ns

Notes:

1. TERA

CT enabled via Control Register.

2. Guaranteed by test.

3. Command word measured from mid-bit crossing

12MHz

BIPHASE IN

CS COMMAND WORD P

RBUSY

t

18a

TERACT

RTRT

MRST

Note:

1. Measured from mid-bit parity crossing.

t

18b

t

18c

t

18d

t

18e

t

18f

t

18g

t

18h

t

18i

Figure 18. Status Output T iming

RTS-32

SS STATUS WORD P

BIPHASE OUT

Figure 19a. Receive Command with Two Data Words

DS DATA WORD P

DS DATA WORD P

BIPHASE IN

COMSTR

T/R

BIPHASE OUT

RBUSY

CS COMMAND WORD P

BIPHASE IN

COMSTR

T/R

RBUSY

DS DATA WORD P DS DATA WORD P

CS = Command sync
SS = Status sync
DS = Data sync
P = Parity

1

23

Notes:

1. Burst of 4 DMAs: read command pointer , store command w ord, update command pointer, read data word pointer.

2. Burst of 1 DMA: read data word.

3. Burst of 2 DMAs: read data word, update data word pointer.

4. Approximately 560ns per DMA access.

TERACT

VALMSG

TERA

CT

VALMSG

Notes:

1. Burst of 5 DMAs: read command pointer , store command word, update command pointer, read data word pointer, store
command word.

2. Burst of 1 DMA: store data word.

3. Burst of 2 DMAs: store data word, update data word pointer.

4. Approximately 560ns per DMA access.

SS P STATUS WORD

1

23

CS COMMAND WORD

Figure 19b. Transmit Command with Two Data Words

RTS-33

UT1760A

RTS

ADDR(9:0)

DATA(15:0)

CONTROL

UT63M125

1553 TRANSCEIVER

1553 BUS A

1553 BUS B

Figure 20a. RTS General System Diagram (Idle low interface)

CHANNEL A

CHANNEL B

RTS

RAO
RAZ

TAO
TAZ

RBO
RBZ

TBO
TBZ

TIMERON

UTMC

63M125

CHANNEL A

CHANNEL B

TXINHB

TXINHB

RXOUT
RXOUT

TXIN
TXIN

RXOUT
RXOUT

TXIN
TXIN

HOST

SUBSYSTEM

Figure 20b. RTS Transceiver Interface Diagram

RTS-34

7.0 PACKAGE OUTLINE DRAWING

ILLEGAL
COMMAND
DECODER

RTS

Figure 21. Mode Code/Subaddress Illegalization Circuit

MC/SA

MCSA0
MCSA1

MCSA2
MCSA3
MCSA4

COMSTR
BRDCST

T/R
RTRT

ILLCOM

RTS-35

K1 RD/WR
K2 CS
K3 MRST
K4 RTA3
K5 RTA1
K6 RTPTY
K7 RBO
K8 RAO
K9 ILLCOM
K10 DATA1
K11 DATA2

L2 12MHz
L3 RTA4
L4 RTA2
L5 RTA0
L6 RBZ
L7 RAZ
L8 VALMSG

L

K

J

H

G

F

E

D

C

B

A

1234567891011

A2 A3 A4 A5 A6 A7 A8 A9 A10

B1

B2

B3 B4 B5 B6 B7 B8 B9

B10 B11

C1

C2

C10 C11

D1

D2

D10

D11

E1 E2

E10 E11

F1

F2

F10

F11

G1

G2

G10

G11

H1

H2

H10

H11

L2 L3 L4 L5 L6 L7 L8 L9

L10

K1

K2 K3 K4 K5 K6 K7 K8 K9

K10 K11

J1

J2

J10 J11

A2 MCSA1
A3 MCSA2
A4 MCSA4
A5 MERR
A6 TERA

CT or

DSCNCT
A7 BRDCST
A8 2MHz
A9 TBZ
A10 TAZ

B1 MC/SA
B2 MCSA0
B3 MCSA3
B4 T/R
B5 TXERR
B6 TIMERON
B7 RTRT
B8 COMSTR

C1 ADDR9
C2 RBUSY
C10 DATA13
C11 DATA14

D1 ADDR7
D2 ADDR8
D10 DATA11
D11 DATA12

E1 V

DD

E2 ADDR6
E10 DATA9
E11 DATA10

F1 ADDR5

G1 ADDR3
G2 ADDR4
G10 DATA7
G11 V

SS

H1 ADDR1
H2 ADDR2
H10 DATA5
H11 DATA6

J1 CTRL
J2 ADDR0

Figure 22. UT1760A RTS Pingrid Array Configuration (Bottom View)

Packaging-1

Package Selection Guide

NOTE:

1. 84LCC package is not available radiation-hardened.

Product

RTI RTMP RTR BCRT BCRTM BCRTMP RTS XCVR

24-pin DIP
(single cavity)

X

36-pin DIP
(dual cavity)

X

68-pin PGA X X
84-pin PGA X X X X

1

144-pin PGA X
84-lead LCC X X X

1

36-lead FP
(dual cavity)
(50-mil ctr)

X

84-lead FP X X
132-lead FP X X

Packaging-2

1

144-Pin Pingrid Array

E

1.565 ± 0.025

-B-

D

1.565 ± 0.025

-A-

0.080 REF.
(2 Places)

0.040 REF.

0.100 REF.
(4 Places)

A

0.130 MAX.
Q

0.050 ± 0.010

A

A

L

0.130 ±0.010

PIN 1 I.D.

(Geometry Optional)

-C-

(Base Plane)

b

0.018 ± 0.002

0.030

0.010

C A B
C

SIDE VIEW

TOP VIEW

0.003 MIN. TYP.

D1/E1

1.400

0.100

TYP.

e

PIN 1 I.D.

(Geometry Optional)

2

R
P
N
M
L
K
J
H
G
F
E
D

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Notes:

1. True position applies to pins at base plane (datum C).

2. True position applies at pin tips.

3. All package finishes are per MIL-M-38510.

4. Letter designations are for cross-reference to MIL-M-38510.

BOTTOM VIEW

Packaging-3

132-Lead Flatpack (25-MIL Lead Spacing)

SIDE VIEW

TOP VIEW

BOTTOM VIEW A-A

DETAIL A

0.018 MAX. REF.

0.014 MAX. REF.
(At Braze Pads)

L

0.250
MIN.
REF.

LEAD KOVAR

SEE DETAIL A

A

A

C

0.005

+ 0.002

- 0.001

A

0.110

0.006

D1/E1

0.950 ± 0.015 SQ.

D/E

1.525 ± 0.015 SQ.

PIN 1 I.D.

(Geometry

Optional)

e

0.025

Notes:

1. All package finishes are per MIL-M-38510.

2. Letter designations are for cross-reference to MIL-M-38510.

S1

0.005 MIN. TYP.

Packaging-4

84-LCC

SIDE VIEW

TOP VIEW

BOTTOM VIEW A-A

Notes:

1. All package finishes are per MIL-M-38510.

2. Letter designations are for cross-reference to MIL-M-38510.

L/L1

0.050 ± 0.005 TYP.

B1

0.025 ± 0.003

e

0.050

e1

0.015 MIN.

PIN 1 I.D.

(Geometry Optional)

J

0.020 X 455 REF.

h

0.040 x 45_
REF. (3 Places)

D/E

1.150 ± 0.015 SQ.

A

0.115 MAX.
A1

0.080 ± 0.008

A

A

PIN 1 I.D.
(Geometry Optional)

Packaging-5

84-Lead Flatpack (50-MIL Lead Spacing)

SIDE VIEW

TOP VIEW

BOTTOM VIEW A-A

D/E

1.810 ± 0.015 SQ.

Notes:

1. All package finishes are per MIL-M-38510.

2. Letter designations are for cross-reference to MIL-M-38510.

DETAIL A

D1/E1

1.150 ± 0.012 SQ.

A

0.110

0.060

A

A

C

0.007 ± 0.001

LEAD KOVAR

SEE DETAIL A

PIN 1 I.D.

(Geometry

Optional)

b

0.016 ± 0.002

L

0.260
MIN.
REF.

S1

0.005 MIN. TYP.

0.050

e

0.014 MAX.

REF.

(At Braze Pads)

0.018 MAX. REF.

Packaging-6

84-Pin Pingrid Array

SIDE VIEW

TOP VIEW

BOTTOM VIEW A-A

D

1.100 ± 0.020

E

1.100 ± 0.020

-B-

-A-

A

0.130 MAX.
Q

0.050 ± 0.010

L

0.130 ± 0.010

A

A

-C-

(Base Plane)

b

0.018 ± 0.002

PIN 1 I.D.
(Geometry Optional)

1.000

D1/

e

0.100

TYP.

0.003 MIN.

L
K
J
H
G
F
E
D

1 2 3 4 5 6 7 8 9 10 11

Notes:

1. True position applies to pins at base plane (datum C).

2. True position applies at pin tips.

3. All packages finishes are per MIL-M-38510.

4. Letter designations are for cross-reference to MIL-M-38510.

PIN 1 I.D.

(Geometry Optional)

1

0.030

0.010

C A B
C

2

Packaging-7

SIDE VIEW

TOP

BOTTOM VIEW A-A

D

1.100 ± 0.020

PIN 1 I.D.
(Geometry Optional)

L
K
J
H
G
F
E
D
C
B
A

1 2 3 4 5 6 7 8 9 10 11

Notes:

1 True position applies to pins at base plane (datum C).
2 True position applies at pin tips.

3. All packages finishes are per MIL-M-38510.

4. Letter designations are for cross-reference to MIL-M-38510.

PIN 1 I.D.

(Geometry Optional)

D1/E1

1.00

0.003 MIN. TYP.

e

0.100
TYP.

A

0.130 MAX.
Q

0.050 ± 0.010

L

0.130 ± 0.010

A

A

-A-

-B-

E

1.100 ± 0.020

-C-

(Base Plane)

68-Pin Pingrid Array

0.030

0.010 C

A

B

1

2

C

∅
∅

b

0.010 ± 0.002

Packaging-8

D

1.800 ± 0.025

36-Lead Flatpack, Dual Cavity (100-MIL Lead Spacing)

TOP VIEW

END VIEW

E

0.750 ± 0.015

Notes:

1 All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.

3. Letter designations are for cross-reference to MIL-M-38510.

PIN 1 I.D.

(Geometry Optional)

L

0.490
MIN.

b

0.015 ± 0.002

e

0.10

c

0.008

+ 0.002

- 0.001

Q

0.080 ± 0.010
(At Ceramic Body)

A

0.130 MAX.

Packaging-9

36-Lead Flatpack, Dual Cavity (50-MIL Lead Spacing)

TOP

E

0.700 + 0.015

Notes:

1. All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.

3. Letter designations are for cross-reference to MIL-M-38510.

c

0.007

+ 0.002

- 0.001

Q

0.070 + 0.010
(At Ceramic Body)

A

0.100 MAX.

END

D

1.000 ± 0.025

b

0.016 + 0.002

e

0.050

PIN 1 I.D
(Geometry Optional)

L

0.330
MIN.

Packaging-10

36-Lead Side-Brazed DIP, Dual Cavity

TOP VIEW

END VIEW

E

0.590 ± 0.012

Notes:

1. All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.

3. Letter designations are for cross-reference to MIL-M-38510.

PIN 1 I.D.

(Geometry Optional)

SIDE VIEW

S1

0.005 MIN.

D

1.800 ± 0.025

S2

0.005 MAX.

e

0.100

A

0.155 MAX.

L/L1

0.150 MIN.

C

0.010

+ 0.002

- 0.001

E1

0.600 + 0.010
(At Seating Plane)

b

0.018 ± 0.002

Packaging-11

E

0.590 ± 0.015

S1

0.005 MIN.

S2

0.005 MAX.

TOP VIEW

PIN 1 I.D.

(Geometry Optional)

D

1.200 ± 0.025

SIDE VIEW

A

0.140 MAX.

L/L1

0.150 MIN.

0.100

e

Notes:

1. All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.

3. Letter designations are for cross-reference to MIL-M-38510.

END VIEW

C

0.010

+ 0.002

- 0.001

E1

0.600 + 0.010
(At Seating Plane)

b

0.018 ± 0.002

24-Lead Side-Brazed DIP, Single Cavity

ORDERING INFORMATION

UT1553B RTS Remote Terminal for Stores: S

Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional

Case Outline:
(X) = 68 pin PGA

Class Designator:
(-) = Blank or No field is QML Q

Drawing Number: 8957501

Total Dose:
(-) = None

Federal Stock Class Designator: No options

5962 * * * * *

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).

3. For QML Q product, the Q designator is intentionally left blank in the SMD number (e.g. 5962-8957501XC).

UT1553B RTS Remote Terminal for Stores

Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional

Package Type:
(G) = 68 pin PGA

UTMC Core Part Number

No UT Part
Number- * *

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).