Page 1
TL/F/9581
54F/74F651
#
54F/74F652 Transceivers/Registers
December 1994
54F/74F651#54F/74F652
Transceivers/Registers
General Description
These devices consist of bus transceiver circuits with
D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or
from internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to HIGH logic level. Output Enable pins (OEAB, OEBA
) are
provided to control the transceiver function.
Features
Y
Independent registers for A and B buses
Y
Multiplexed real-time and stored data
Y
Choice of non-inverting and inverting data paths
Ð ’F651 inverting
Ð ’F652 non-inverting
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F651SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
54F651SDM (Note 2) J24F 24-Lead (0.300×Wide) Ceramic Dual-In-Line
74F651SC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC
54F651FM (Note 2) W24C 24-Lead Cerpack
54F651LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C
74F652SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
54F652SDM (Note 2) J24F 24-Lead (0.300×Wide) Ceramic Dual-In-Line
74F652SC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC
54F652FM (Note 2) W24C 24-Lead Cerpack
54F652LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C
Note 1:Devices also available in 13×reel. Use suffixeSCX
Note 2:Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB
Connection Diagrams
Pin Assignment
DIP, SOIC and Flatpak
TL/F/9581– 3
Pin Assignment
for LCC
TL/F/9581– 4
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Page 2
Logic Symbols
IEEE/IEC
’F651
TL/F/9581– 1
’F651
TL/F/9581– 2
IEEE/IEC
’F652
TL/F/9581– 10
’F652
TL/F/9581– 11
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
A0–A7,B0–B7A and B Inputs/ 1.0/1.0 20 mA/b0.6 mA
TRI-STATE
É
Outputs 600/106.6 (80)b12 mA/64 mA (48 mA)
CPAB, CPBA Clock Inputs 1.0/1.0 20 mA/
b
0.6 mA
SAB, SBA Select Inputs 1.0/1.0 20 m A/b0.6 mA
OEAB, OEBA
Output Enable Inputs 1.0/1.0 20 mA/b0.6 mA
2
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Logic Diagrams
’F652
TL/F/9581– 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
’F651
TL/F/9581– 12
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in
Figure 1
demonstrate the four fundamental
bus-management functions that can be performed with the
Octal bus transceivers and receivers.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW to HIGH transitions at the appro-
priate Clock Inputs (CPAB, CPBA) regardless of the Select
or Output Enable Inputs. When SAB and SBA are in the real
time transfer mode, it is also possible to store data without
using the internal D flip-flops by simultaneously enabling
OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two
sets of bus lines are in a HIGH impedance state, each set of
bus lines will remain at its last state.
Note A: Real-Time
Transfer Bus B to Bus A
TL/F/9581– 6
OEAB OEBA CPAB CPBA SAB SBA
LLXXXL
Note B: Real-Time
Transfer Bus A to Bus B
TL/F/9581– 7
OEAB OEBA CPAB CPBA SAB SBA
HHXXLX
Note C: Storage
TL/F/9581– 8
OEAB OEBA CPAB CPBA SAB SBA
XHLXXX
LXXLXX
LHLLXX
Note D: Transfer Storage
Data to A or B
TL/F/9581– 9
OEAB OEBA CPAB CPBA SAB SBA
H L HorL HorL H X
FIGURE 1
Inputs Inputs/Outputs (Note 1) Operating Mode
OEAB OEBA CPAB CPBA SAB SBA A0thru A
7
B0thru B
7
L H HorL HorL X X
Input Input
Isolation
LHLL X X Store A and B Data
XHLH or L X X Input Not Specified Store A, Hold B
HHLL X X Input Output Store A in Both Registers
L X HorL L X X Not Specified Input Hold A, Store B
LLLL X X Output Input Store B in Both Registers
LLXXXL
Output Input
Real-Time B Data to A Bus
L L X H or L X H Store B Data to A Bus
HHXXLX
Input Output
Real-Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output
Stored A Data to B Bus and
Stored B Data to A Bus
HeHIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
L
e
LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the
bus pins will be stored on every LOW to HIGH transition on the clock inputs.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b
65§Ctoa150§C
Ambient Temperature under Bias
b
55§Ctoa125§C
Junction Temperature under Bias
b
55§Ctoa175§C
Plastic
b
55§Ctoa150§C
VCCPin Potential to
Ground Pin
b
0.5V toa7.0V
Input Voltage (Note 2)
b
0.5V toa7.0V
Input Current (Note 2)
b
30 mA toa5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0.5V to V
CC
TRI-STATE Output
b
0.5V toa5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55§Ctoa125§C
Commercial 0
§
Ctoa70§C
Supply Voltage
Military
a
4.5V toa5.5V
Commercial
a
4.5V toa5.5V
DC Electrical Characteristics
Symbol Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1.2 V Min I
IN
eb
18 mA (Non I/O Pins)
V
OH
Output HIGH 54F 10% V
CC
2.0
V Min
I
OH
eb
12 mA (An,Bn)
Voltage 74F 10% V
CC
2.0 I
OH
eb
15 mA (An,Bn)
V
OL
Output LOW 54F 10% V
CC
0.55
V Min
I
OL
e
48 mA (An,Bn)
Voltage 74F 10% V
CC
0.55 I
OL
e
64 mA (An,Bn)
I
IH
Input HIGH 54F 20.0
mA Max
V
IN
e
2.7V
Current 74F 5.0 (Non I/O Pins)
I
BVI
Input HIGH Current 54F 100
mA Max
V
IN
e
7.0V
Breakdown Test 74F 7.0
I
BVIT
Input HIGH Current 54F 1.0
mA Max
V
IN
e
5.5V
Breakdown (I/O) 74F 0.5 (A
n,Bn
)
I
CEX
Output HIGH 54F 250
mA Max
V
OUT
e
V
CC
Leakage Current 74F 50
V
ID
Input Leakage
74F 4.75 V 0.0
I
ID
e
1.9 mA
Test All Other Pins Grounded
I
OD
Output Leakage
74F 3.75 m A 0.0
VI
IOD
e
150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current
b
0.6 mA Max V
IN
e
0.5V (Non I/O Pins)
I
IH
a
I
OZH
Output Leakage Current 70 mA Max V
OUT
e
2.7V (An,Bn)
I
IL
a
I
OZL
Output Leakage Current
b
650 mA Max V
OUT
e
0.5V (An,Bn)
I
OS
Output Short-Circuit Current
b
100
b
225 mA Max V
OUT
e
0V
I
ZZ
Bus Drainage Test 500 mA 0.0V V
OUT
e
5.25V
I
CCH
Power Supply Current 105 135 mA Max V
O
e
HIGH
I
CCL
Power Supply Current 118 150 mA Max V
O
e
LOW
I
CCZ
Power Supply Current 115 150 mA Max V
O
e
HIGH Z
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AC Electrical Characteristics
74F 54F 74F
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com
Symbol Parameter V
CC
ea
5.0V
C
L
e
50 pF C
L
e
50 pF
Units
C
L
e
50 pF
Min Max Min Max Min Max
f
max
Max. Clock Frequency 90 75 90 MHz
t
PLH
Propagation Delay 2.0 7.0 2.0 8.5 2.0 8.0
ns
t
PHL
Clock to Bus 2.0 8.0 2.0 9.5 2.0 9.0
t
PLH
Propagation Delay 2.0 8.5 1.0 9.0 2.0 9.0
ns
t
PHL
Bus to Bus (’F651) 1.0 7.5 1.0 8.0 1.0 8.0
t
PLH
Propagation Delay 1.0 7.0 1.0 8.0 1.0 7.5
ns
t
PHL
Bus to Bus (’F652) 1.0 6.5 1.0 8.0 1.0 7.0
t
PLH
Propagation Delay 2.0 8.5 2.0 11.0 2.0 9.5
ns
t
PHL
SBA or SAB to A or B 2.0 8.0 2.0 10.0 2.0 9.0
AC Operating Requirements
74F 54F 74F
Symbol Parameter
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com Units
V
CC
ea
5.0V
Min Max Min Max Min Max
t
PZH
Enable Time 2.0 9.5 2.0 10.0 2.0 10.0
t
PZL
*OEBA to A 2.0 12.0 2.0 10.0 2.0 12.5
t
PHZ
Disable Time 1.0 7.5 1.0 9.0 1.0 8.0
ns
t
PLZ
*OEBA to A 2.0 8.5 1.0 9.0 2.0 9.0
t
PZH
Enable Time 2.0 9.5 2.0 10.0 2.0 10.0
t
PZL
OEAB to B 3.0 13.0 2.0 12.0 3.0 14.0
t
PHZ
Disable Time 2.0 9.0 1.0 9.0 2.0 10.0
ns
t
PLZ
OEAB to B 2.0 10.5 1.0 12.0 2.0 11.0
ts(H) Setup Time, HIGH or 5.0 5.0 5.0
ns
t
s
(L) LOW, Bus to Clock 5.0 5.0 5.0
th(H) Hold Time, HIGH or 2.0 2.5 2.0
ns
t
h
(L) LOW, Bus to Clock 2.0 2.5 2.0
tw(H) Clock Pulse Width 5.0 5.0 5.0
ns
t
w
(L) HIGH or LOW 5.0 5.0 5.0
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 651/652 S C X
Temperature Range Family Special Variations
74F
e
Commercial QBeMilitary grade device with
54F
e
Military environmental and burn-in
processing
Device Type
X
e
Devices shipped in 13×reel
Package Code
Temperature Range
SP
e
Slim Plastic DIP
C
e
Commercial (0§Ctoa70§C)
SD
e
Slim Ceramic DIP
M
e
Military (b55§Ctoa125§C)
S
e
Small Outline (SOIC)
6
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7
Page 8
Physical Dimensions inches (millimeters)
28 Lead Ceramic Leadless Chip Carrier, Type C
NS Package Number E28A
24 Lead (0.300×Wide) Ceramic Dual-In-Line Package (SD)
NS Package Number J24F
8
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Physical Dimensions inches (millimeters) (Continued)
24 Lead (0.300×Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M24B
24 Lead (0.300×Wide) Molded Dual-In-Line Package (SP)
NS Package Number N24C
9
Page 10
54F/74F651
#
54F/74F652 Transceivers/Registers
Physical Dimensions inches (millimeters) (Continued)
24 Lead Cerpack
NS Package Number W24C
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SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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