Datasheet 5962-8769701SRA, 5962-8769701SSA, 5962-8769701S2A, 5962-8769701MSA, 5962-8769701MRA Datasheet (NSC)

54AC377•54ACT377
Octal D Flip-Flop with Clock Enable

General Description

The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff­ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.

The register is fully edge-triggered. The state of each D in­put, one setup time before the LOW-to-HIGH clock transi­tion, is transferred to the corresponding flip-flop’s Q output.
The CE inputmust be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.

Features

n ICCreduced by 50

%

n Ideal for addressable register applications
n Clock enable for address and data synchronization

applications

n Eight edge-triggered D flip-flops
n Buffered common clock
n Outputs source/sink 24 mA
n See ’273 for master reset version
n See ’373 for transparent latch version
n See ’374 for TRI-STATE

®

version

n ’ACT377 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)

—’AC377: 5962-88702
—’ACT377: 5962-87697

Logic Symbols

Pin

Names

Description

D

0–D7

Data Inputs

CE

Clock Enable (Active LOW)

Q

0–Q7

Data Outputs

CP Clock Pulse Input

TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT

®

is a registered trademark of Fairchild Semiconductor Corporation.

DS100290-1

IEEE/IEC

DS100290-2

February 1999

54AC377

•

54ACT377 Octal D Flip-Flop with Clock Enable

© 1999 National Semiconductor Corporation DS100290 www.national.com

Connection Diagrams

Mode Select-Function Table

Operating Mode Inputs Outputs

CP CE

D

n

Q

n

Load ‘1’

N

LH H

Load ‘0’

N

LL L

Hold (Do Nothing)

N

H X No Change

X H X No Change

H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial

N

=

LOW-to-HIGH Clock Transition

Logic Diagram

Pin Assignment

for DIP and Flatpak

DS100290-3

Pin Assignment

for LCC

DS100290-4

DS100290-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

CC

) −0.5V to +7.0V

DC Input Diode Current (I

IK

)

V

I

=

−0.5V −20 mA

V

I

=

V

CC

+ 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC+ 0.5V

DC Output Diode Current (I

OK

)

V

O

=

−0.5V −20 mA

V

O

=

V

CC

+ 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC+ 0.5V

DC Output Source

or Sink Current (I

O

)

±

50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

)

±

50 mA

Storage Temperature (T

STG

) −65˚C to +150˚C

Junction Temperature (T

J

)

CDIP 175˚C

Recommended Operating
Conditions

Supply Voltage (VCC)

’AC 2.0V to 6.0V
’ACT 4.5V to 5.5V

Input Voltage (V

I

) 0VtoV

CC

Output Voltage (VO) 0VtoV

CC

Operating Temperature (TA)

54AC/ACT −55˚C to +125˚C

Minimum Input Edge Rate (∆V/∆t)

’AC Devices
V

IN

from 30%to 70%of V

CC

V

CC

@

3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

’ACT Devices
V

IN

from 0.8V to 2.0V

V

CC

@

4.5V, 5.5V 125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom­mend operation of FACT

®

circuits outside databook specifications.

Note 2: See individual datasheets for those devices which differ from the
typical input rise and fall times noted here.

DC Characteristics for ’AC Family Devices

54AC

Symbol Parameter V

CC

T

A

=

Units Conditions

(V) −55˚C to +125˚C

Guaranteed Limits

V

IH

Minimum High Level 3.0 2.1 V

OUT

=

0.1V

Input Voltage 4.5 3.15 V or V

CC

− 0.1V

5.5 3.85

V

IL

Maximum Low Level 3.0 0.9 V

OUT

=

0.1V

Input Voltage 4.5 1.35 V or V

CC

− 0.1V

5.5 1.65

V

OH

Minimum High Level 3.0 2.9 I

OUT

=

−50 µA

Output Voltage 4.5 4.4 V

5.5 5.4
(Note 3)
V

IN

=

V

IL

or V

IH

3.0 2.4 I

OH

=

−12 mA

4.5 3.7 V I

OH

=

−24 mA

5.5 4.7 I

OH

=

−24 mA

V

OL

Maximum Low Level 3.0 0.1 I

OUT

=

50 µA

Output Voltage 4.5 0.1 V

5.5 0.1
(Note 3)
V

IN

=

V

IL

or V

IH

3.0 0.50 I

OL

=

12 mA

4.5 0.50 V I

OL

=

24 mA

5.5 0.50 I

OL

=

24 mA

I

IN

Maximum Input 5.5

±

1.0 µA V

I

=

V

CC

, GND

Leakage Current

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DC Characteristics for ’AC Family Devices (Continued)

54AC

Symbol Parameter V

CC

T

A

=

Units Conditions

(V) −55˚C to +125˚C

Guaranteed Limits

I

OLD

(Note 4) 5.5 50 mA V

OLD

=

1.65V Max

Minimum Dynamic

I

OHD

Output Current 5.5 −50 mA V

OHD

=

3.85V Min

I

CC

Maximum Quiescent 5.5 80.0 µA V

IN

=

V

CC

Supply Current or GND

Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I

IN

and I

CC

@

3.0V are guaranteed to be less than or equal to the respective limit@5.5V VCC.

I

CC

for 54AC@25˚C is identical to 74AC@25˚C.

DC Characteristics for ’ACT Family Devices

54ACT

Symbol Parameter V

CC

T

A

=

Units Conditions

(V) −55˚C to +125˚C

Guaranteed Limits

V

IH

Minimum High Level 4.5 2.0 V V

OUT

=

0.1V

Input Voltage 5.5 2.0 or V

CC

− 0.1V

V

IL

Maximum Low Level 4.5 0.8 V V

OUT

=

0.1V

Input Voltage 5.5 0.8 or V

CC

− 0.1V

V

OH

Minimum High Level 4.5 4.4 V I

OUT

=

−50 µA

Output Voltage 5.5 5.4

(Note 6)
V

IN

=

V

IL

or V

IH

4.5 3.70 V I

OH

=

−24 mA

5.5 4.70 I

OH

=

−24 mA

V

OL

Maximum Low Level 4.5 0.1 V I

OUT

=

50 µA

Output Voltage 5.5 0.1

(Note 6)
V

IN

=

V

IL

or V

IH

4.5 0.50 V I

OL

=

24 mA

5.5 0.50 I

OL

=

24 mA

I

IN

Maximum Input 5.5

±

1.0 µA V

I

=

V

CC

, GND

Leakage Current

I

CCT

Maximum 5.5 1.6 mA V

I

=

V

CC

− 2.1V

I

CC

/Input

I

OLD

(Note 7) 5.5 50 mA V

OLD

=

1.65V Max

Minimum Dynamic

I

OHD

Output Current 5.5 −50 mA V

OHD

=

3.85V Min

I

CC

Maximum Quiescent 5.5 80.0 µA V

IN

=

V

CC

Supply Current or GND

Note 6:*All outputs loaded; thresholds on input associated with output under test.
Note 7:

†

Maximum test duration 2.0 ms, one output loaded at a time.

Note 8: I

CC

for 54ACT@25˚C is identical to 74ACT@25˚C.

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AC Electrical Characteristics

54AC

V

CC

T

A

=

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 9) C

L

=

50 pF

Min Max

f

max

Maximum Clock 3.3 75 MHz
Frequency 5.0 95

t

PLH

Propagation Delay 3.3 1.0 14.0 ns
CP to Q

n

5.0 1.5 10.0

t

PHL

Propagation Delay 3.3 1.0 15.0 ns
CP to Q

n

5.0 1.5 11.0

Note 9: Voltage Range 3.3 is 3.3V±0.3V
Voltage Range 5.0 is 5.0V

±

0.5V

AC Operating Requirements

54AC

V

CC

T

A

=

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 10) C

L

=

50 pF

Guaranteed

Minimum

t

s

Setup Time, HIGH or LOW 3.3 7.5 ns
D

n

to CP 5.0 6.0

t

h

Hold Time, HIGH or LOW 3.3 1.5 ns
D

n

to CP 5.0 2.5

t

s

Setup Time, HIGH or LOW 3.3 9.5 ns
CE to CP

5.0 6.0

t

h

Hold Time, HIGH or LOW 3.3 1.0 ns
CE to CP

5.0 2.0

t

w

CP Pulse Width 3.3 6.5 ns
HIGH or LOW 5.0 5.0

Note 10: Voltage Range 3.3 is 3.0V±0.3V
Voltage Range 5.0 is 5.0V

±

0.5V

AC Electrical Characteristics

54ACT

V

CC

T

A

=

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 11) C

L

=

50 pF

Min Max

f

max

Maximum Clock 5.0 85 MHz
Frequency

t

PLH

Propagation Delay 5.0 1.5 11.0 ns
CP to Q

n

t

PHL

Propagation Delay 5.0 1.5 12.0 ns
CP to Q

n

Note 11: Voltage Range 5.0 is 5.0V±0.5V

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AC Operating Requirements

54ACT

V

CC

T

A

=

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note

12)

C

L

=

50 pF

Guaranteed

Minimum

t

s

Setup Time, HIGH or LOW 5.0 7.0 ns
D

n

to CP

t

h

Hold Time, HIGH or LOW 5.0 1.0 ns
D

n

to CP

t

s

Setup Time, HIGH or LOW 5.0 7.0 ns
CE to CP

t

h

Hold Time, HIGH or LOW 5.0 1.0 ns
CE to CP

t

w

CP Pulse Width 5.0 5.5 ns
HIGH or LOW

Note 12: Voltage Range 5.0 is 5.0V±0.5V

Capacitance

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF V

CC

=

OPEN

C

PD

Power Dissipation 90.0 pF V

CC

=

5.0V

Capacitance

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Physical Dimensions inches (millimeters) unless otherwise noted

20 Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

20 Lead Ceramic Dual-In-Line Package (D)

NS Package Number J20A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE­VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI­CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys­tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail­ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.

2. A critical component is any component of a life support
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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20 Lead Ceramic Flatpak (F)

NS Package Number W20A

54AC377

•

54ACT377 Octal D Flip-Flop with Clock Enable

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.