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54FCT373
Octal Transparent Latch with TRI-STATE
®
Outputs
General Description
The ’FCT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH the bus output is in the high
impedance state.
Features
n TRI-STATE outputs for bus interfacing
n TTL input and output level compatible
n CMOS power consumption
n Output sink capability of 32 mA, source capability of
12 mA
n Standard Microcircuit Drawing (SMD) 5962-8764401
Ordering Code
Military Package Number Package Description
54FCT373DMQB J20A 20-Lead Ceramic Dual-In-Line
54FCT373FMQB W20A 20-Lead Cerpack
54FCT373LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
(Active HIGH)
OE
Output Enable Input
(Active LOW)
O
0–O7
TRI-STATE Latch
Outputs
TRI-STATE®is a registered trademarkof National Semiconductor Corporation.
Pin Assignment
for DIP and Flatpak
DS100957-1
Pin Assignment
for LCC
DS100957-2
October 1999
54FCT373 Octal Transparent Latch with TRI-STATE Outputs
© 1999 National Semiconductor Corporation DS100957 www.national.com
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Functional Description
The ’FCT373 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW, the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Inputs Output
LE OE
D
n
O
n
HLH H
HLL L
LLXO
n
(no change)
XHX Z
H
=
HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance State
Logic Diagram
DS100957-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
54FCT373
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias
Ceramic −55˚C to +175˚C
V
CC
Pin Potential to
Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State −0.5V to +5.5V
in the HIGH State −0.5V to V
CC
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Military −55˚C to +125˚C
Supply Voltage
Military +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol Parameter FCT240
Units V
CC
Conditions
Min Max
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min I
IN
=
−18 mA
V
OH
Output HIGH
Voltage
54FCT 4.3 V Min I
OH
=
−300 uA
54FCT 2.4 V Min I
OH
=
−12 mA
V
OL
Output LOW
Voltage
54FCT 0.2 V Min I
OL
=
300 µA
54FCT 0.5 V Min I
OL
=
32 mA
I
IH
Input HIGH Current 5 µA Max V
IN
=
5.5V
I
IL
Input LOW Current −5 µA Max V
IN
=
0.0V
I
OZH
High Impedance Output Current 10 µA Max V
IN
=
5.5V
I
OZL
High Impedance Output Current -10 µA Max V
IN
=
0.0V
I
OS
Output Short-Circuit Current −60 mA Max V
OUT
=
0.0V
I
CCQ
Power Supply Current 1.5 mA Max VIN= 0.2V or VIN= 5.3V
∆I
CC
Power Supply Current 2.0 mA Max VIN= 3.4V
I
CCT
Total Power Supply Current
5.6 mA Max
V
IN
=
3.4V or V
IN
=GND, OE =
GND, fI= 10Mhz, outputs open,
one bit toggling, 50%duty cycle
4.0 mA Max
V
IN
=
5.3V or V
IN
= 0.2V,OE =
GND, fI= 10Mhz, outputs open,
one bit toggling, 50%duty cycle
I
CCD
Dynamic I
CC
0.25 mA/MHz Max
Outputs Open, OE=GND, one bit
toggling, 50%duty Cycle
54FCT373
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AC Electrical Characteristics
Symbol Parameter 54FCT Units Fig.
No.
T
A
=
−55˚C to +125˚C
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
Min Max
t
PLH
Propagation Delay 1.5 8.5 ns
Figure 4
t
PHL
Dnto O
n
1.5 8.5
t
PLH
Propagation Delay 2.0 15.0 ns
Figure 4
t
PHL
LE to O
n
2.0 15.0
t
PZH
Output Enable Time 1.5 13.5 ns
Figure 6
t
PZL
1.5 13.5
t
PHZ
Output Disable Time 1.5 12.5 ns
Figure 6
t
PLZ
1.5 12.5
AC Operating Requirements
Symbol Parameter 54FCT Units Fig.
No.
T
A
=
−55˚C to +125˚C
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
Min Max
t
s
(H) Setup Time, HIGH 2.0 ns
Figure 7
ts(L) or LOW Dnto LE 2.0
t
h
(H) Hold Time, HIGH 3.0 ns
Figure 7
th(L) or LOW Dnto LE 3.0
t
w
(H) Pulse Width, 6.0 ns
Figure 5
LE HIGH
Capacitance
Symbol Parameter Max Units Conditions
(T
A
=
25˚C)
C
IN
Input Capacitance 10 pF V
CC
=
0V
C
OUT
(Note 3) Output Capacitance 12 pF V
CC
=
5.0V
Note 3: C
OUT
is measured at frequency f=1 MHz, per MIL-STD-883B, Method 3012.
54FCT373
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AC Loading
DS100957-4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100957-6
FIGURE 2. Test Input Signal Levels
Amplitude Rep. Rate t
w
t
r
t
f
3.0V 1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100957-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100957-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100957-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100957-9
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
54FCT373
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Chip Carrier (L)
NS Package Number E20A
54FCT373
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Dual-In-Line (D)
NS Package Number J20A
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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www.national.com
54FCT373 Octal Transparent Latch with TRI-STATE Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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