Datasheet 54HC4050RPFI, 54HC4050RPFS, 54HC4050RPFE, 54HC4050RPFB Datasheet (MAXWELL)

54HC4050

CMOS Logic Hex

Non-Inverting Buffers

FEATURES:

• High speed CMOS logic hex non-inverting buffers

•R

AD-PAK® radiation hardened against natural space radia-

tion

• Single Event Effects:

- SEL: > 120 MeV/mg/cm2

• Total dose hardness:

• - > 100 Krad (Si), depending upon space mission

• Package:

-16 Pin R

• Typical propagation delay:

- 6ns at V

• High-to-Low voltage level converter for up to V

• Fanout (over temperature range)

-10 LSTTL loads (Standard Outputs)

-15 LSTTL loads (Bus Driver Outputs)

• Balanced propagation delay and transition times

• Significant power reduction compared to LSTTL logic ICs

• 2V to 6V operation

• High noise immunity

•-N

AD-PAK® Flat Pack

= 5V, CL = 15pF, TA = 25°C

CC

= 30%, NIH = 30% of VCC at VCC = 5V

IL

= 16V

I

Logic Diagram

DESCRIPTION:

Maxwell Technologies' 54HC4050 high speed CMOS Logic
Hex Non-Inverting Buffers features a greater than 100 krad(Si)
total dose tolerance, depending upon space mission. These
parts have a modified input protection structure that enables
them to be used as logic level translators which will convert
high-level logic to a low-level logic while operating off the low­level logic supply. For example, 15V input pulse levels can be
down-converted to 0V to 5V logic levels. The modified input
protection structure protects the input from negative electro­static discharge. The 54HC4050 can be used as simple buff­ers or inverters without level translation.

Maxwell Technologies' patented R
ogy incorporates radiation shielding in the microcircuit pack­age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.

AD-PAK® packaging technol-

AD-PAK provides greater than 100

Memory

1000587

[phone] - Fax: [phone] - www.maxwell.com

12.19.01 Rev 1

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

1

CMOS Logic Hex Non-Inverting Buffers

TABLE 1. 54HC4050 PINOUT DESCRIPTIONS

PIN SYMBOL DESCRIPTION

1VCCPower supply

8V

SS

13, 16 NC Not Connected

3, 5, 7, 9, 11, 14 A - F Inputs

2 G = A Buffered Output

4 H = B Buffered Output

6 I = C Buffered Output

10 J = D Buffered Output

12 K = E Buffered Output

15 L = F Buffered Output

Ground

54HC4050

Memory

TABLE 2. 54HC4050 ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNIT

Storage Temperature T

Operating Temperature Range T

DC Supply Voltage V

DC Input Diode Current
For V

< -0.5V or VI > VCC +0.5V

I

DC Output Diode Current

< -0.5V or VO > VCC +0.5V

For V

O

DC Output Source or Sink Current per Output Pin
For V

> -0.5V or VO < VCC +0.5V

O

or Ground Current ICC or I

DC V

CC

TABLE 3. DELTA LIMITS

PARAMETER VARIATION

I

CC

±10% of specified value in Table 5

S

A

CC

I

IK

I

OK

I

O

GND

-65 150 °C

-55 125 °C

-0.5 7.0 V

-20 +20 mA

-20 +20 mA

-25 +25 mA

-50 +50 mA

1000587

12.19.01 Rev 1

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

2

CMOS Logic Hex Non-Inverting Buffers

TABLE 4. 54HC4050 RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN MAX UNIT

54HC4050

Supply Voltage V

DC Input or output Voltage V

Input Rise and Fall Time
2V

4.5V
6V

Temperature Range T

TABLE 5. 54HC4050 DC ELECTRICAL CHARACTERISTICS

(VCC = 5V ±10%, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT

High Level Output Voltage
CMOS Loads

High Level Output Voltage
TTL Loads

Low Level Output Voltage
CMOS Loads

Low Level Output Voltage
TTL Loads

High Level Input Voltage V

Low Level Input Voltage V

Input Leakage Current I

V

V

VI = VIH or VIL, IO = -0.02mA

OH

V

= 2V

CC

V

= 4.5V

CC

V

= 6V

CC

V

= VIH or VIL, IO = -4mA

I

V

= 4.5V

CC

V

= VIH or VIL, IO = -5.2mA

I

V

= 6V

CC

VI = VIH or VIL, IO = -0.02mA

OL

V

= 2V

CC

V

= 4.5V

CC

V

= 6V

CC

V

= VIH or VIL, IO = 4mA

I

V

= 4.5V

CC

V

= VIH or VIL, IO = 5.2mA

I

V

= 6V

CC

VCC = 2V

IH

V

= 4.5V

CC

V

= 6V

CC

VCC = 2V

IL

V

= 4.5V

CC

V

= 6V

CC

VCC = 6V, VI = VCC or GND +25°C -- ±0.1 µA

I

V

= 6V, VI = 15V +25°C -- ±0.5

CC

I

, V

CC

26V

O

0VCCV

--

ns

1000

500
400

A

-55 125 °C

Memory

V

1.9

4.4

5.9

+25°C 3.98 --

-55 to 125°C 3.7

+25°C 5.48 --

-55 to 125°C 5.2 --

+25°C 0.26 --

-55 to 125°C 0.4 --

+25°C 0.36 --

-55 to 125°C 0.4 --

1.5

3.15

4.2

--

--

--

-55 to 125°C -- ±1

-55 to 125°C -- ±5

--

--

--

0.1

0.1

0.1

--

--

--

0.5

1.35

1.8

V

V

V

1000587

12.19.01 Rev 1

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

3

CMOS Logic Hex Non-Inverting Buffers

TABLE 5. 54HC4050 DC ELECTRICAL CHARACTERISTICS

(VCC = 5V ±10%, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT

54HC4050

Quiescent Device Current I

TABLE 6. 54HC4050 AC ELECTRICAL CHARACTERISTICS

(VCC = 5V ±10%, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL TEST CONDITION MIN MAX UNIT

Propogation Delay
nA to nY

Transition Times
(Figure 1)

t

t

CC

PLH, tPHL

TLH, tTHL

VI = VCC or GND, IO = 0mA
V

= 6V

CC

CL = 50pF
V

= 2V

CC

+25°C -- 2 µA

-55 to 125°C -- 40

+25°C

-55 to 125°C -- 130

= 4.5V +25°C -- 17

V

CC

-55 to 125°C -- 26

V

= 6V +25°C -- 14

CC

-55 to 125°C -- 22

CL = 50pF
V

= 2V

CC

+25°C

-55 to 125°C -- 110

= 4.5V +25°C -- 15

V

CC

-55 to 125°C -- 22

V

= 6V +25°C -- 13

CC

-55 to 125°C -- 19

ns

-- 85

Memory

ns

-- 75

TABLE 7. 54HC4050 CAPACITANCE

ARAMETER SYMBOL TEST CONDITIONS MAX UNIT

P

Input Capacitance C

Power Dissipation Capacitance

2, 3

1. Guaranteed by design.

2. CPD is used to determine the dynamic power consumption, per gate.

D

2

= V

fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

3. P

1000587

I

C

PD

VCC = 5V 35 pF

12.19.01 Rev 1

1

10 pF

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

4

CMOS Logic Hex Non-Inverting Buffers

FIGURE 1. TRANSITION TIMES AND PROPOGATION DELAY TIMES, COMBINATION LOGIC

54HC4050

Memory

1000587

12.19.01 Rev 1

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

5

CMOS Logic Hex Non-Inverting Buffers

54HC4050

Memory

16-PIN RAD-PAK® FLAT PACKAGE

SYMBOL DIMENSION

MIN NOM MAX

A 0.115 0.135 0.150

b 0.015 0.017 0.019

c 0.004 0.005 0.007

D 0.407 0.415 0.423

E 0.275 0.280 0.285

E1 -- -- 0.500

E2 0.150 0.156 0.162

E3 0.030 0.062 --

e 0.050 BSC

L 0.325 0.335 0.345

Q 0.020 0.033 0.045

S1 0.005 0.024 0.045

N16

F16-01

Note: All dimensions in inches

1000587

12.19.01 Rev 1

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

6

CMOS Logic Hex Non-Inverting Buffers

Important Notice:

These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech­nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

54HC4050

Memory

1000587

12.19.01 Rev 1

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

7

CMOS Logic Hex Non-Inverting Buffers

5

)

Product Ordering Options

Model Number

54HC4050

4HC4050

RP

F X

Feature

Screening Flow

Option Details

Monolithic
S = Maxwell Class S
B = Maxwell Class B
E = Engineering (testing @ +25°C
I = Industrial (testing @ -55°C,
+25°C, +125°C)

Memory

Package

F = Flat Pack

1000587

Radiation Feature

Base Product
Nomenclature

12.19.01 Rev 1

RP = R

AD-PAK® package

CMOS Logic Hex Non-Inverting
Buffers

All data sheets are subject to change without notice

8

©2001 Maxwell Technologies.

All rights reserved.