Datasheet 54F676SDMQB, 54F676FMQB, 54F676DMQB Datasheet (NSC)

Page 1
TL/F/9588
54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register
December 1994
54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register
General Description
The ’F676 contains 16 flip-flops with provision for synchro­nous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P
0–P15
) inputs is entered on the falling edge of the
Clock Pulse (CP
) input signal. When M is LOW, data is shift­ed out of the most significant bit position while information present on the Serial (SI) input shifts into the least signifi­cant bit position. A HIGH signal on the Chip Select (CS
)
input prevents both parallel and serial operations.
Features
Y
16-bit parallel-to-serial conversion
Y
16-bit serial-in, serial-out
Y
Chip select control
Y
Slim 24 lead 300 mil package
Commercial Military
Package
Package Description
Number
74F676PC N24A 24-Lead (0.600×Wide) Molded Dual-In-Line
74F676SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
54F676DM (Note 2) J24A 24-Lead (0.600×Wide) Ceramic Dual-In-Line
54F676SDM (Note 2) J24F 24-Lead (0.300×Wide) Ceramic Dual-In-Line
74F676SC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC
54F676FM (Note 2) W24C 24-Lead Cerpack
54F676LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
TL/F/9588– 2
Pin Assignment
for LCC
TL/F/9588– 3
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Page 2
Logic Symbols
TL/F/9588– 1
IEEE/IEC
TL/F/9588– 4
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
P0–P
15
Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA
CS
Chip Select Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
CP
Clock Pulse Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
M Mode Select Input 1.0/1.0 20 mA/
b
0.6 mA SI Serial Data Input 1.0/1.0 20 mA/b0.6 mA SO Serial Output 50/33.3
b
1 mA/20 mA
Functional Description
The 16-bit shift register operates in one of three modes, as indicated in the Shift Register Operations Table.
HOLDÐa HIGH signal on the Chip Select (CS
) input pre-
vents clocking, and data is stored in the sixteen registers.
Shift/Serial LoadÐdata present on the SI pin shifts into the register on the falling edge of CP
. Data enters the Q
0
position and shifts toward Q15on successive clocks, finally appearing on the SO pin.
Parallel LoadÐdata present on P
0–P15
are entered into
the register on the falling edge of CP
. The SO output repre-
sents the Q
15
register output.
To prevent false clocking, CP must be LOW during a LOW­to-HIGH transition of CS
.
Shift Register Operations Table
Control Input
Operating Mode
CS MCP
H X X Hold LLKShift/Serial Load LHKParallel Load
HeHIGH Voltage Level L
e
LOW Voltage Level
X
e
Immaterial
K
e
HIGH-to-LOW Transition
Block Diagram
TL/F/9588– 5
2
Page 3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
b
65§Ctoa150§C
Ambient Temperature under Bias
b
55§Ctoa125§C
Junction Temperature under Bias
b
55§Ctoa175§C
Plastic
b
55§Ctoa150§C
V
CC
Pin Potential to
Ground Pin
b
0.5V toa7.0V
Input Voltage (Note 2)
b
0.5V toa7.0V
Input Current (Note 2)
b
30 mA toa5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0.5V to V
CC
TRI-STATEÉOutput
b
0.5V toa5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
Free Air Ambient Temperature
Military
b
55§Ctoa125§C
Commercial 0
§
Ctoa70§C
Supply Voltage
Military
a
4.5V toa5.5V
Commercial
a
4.5V toa5.5V
DC Electrical Characteristics
Symbol Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1.2 V Min I
IN
eb
18 mA
V
OH
Output HIGH 54F 10% V
CC
2.5 I
OH
eb
1mA
Voltage 74F 10% V
CC
2.5 V Min I
OH
eb
1mA
74F 5% V
CC
2.7 I
OH
eb
1mA
V
OL
Output LOW 54F 10% V
CC
0.5 V Min
I
OL
e
20 mA
Voltage 74F 10% V
CC
0.5 I
OL
e
20 mA
I
IH
Input HIGH 54F 20.0
mA Max
V
IN
e
2.7V
Current 74F 5.0
I
BVI
Input HIGH Current 54F 100
mA Max
V
IN
e
7.0V
Breakdown Test 74F 7.0
I
CEX
Output HIGH 54F 250
mA Max
V
OUT
e
V
CC
Leakage Current 74F 50
V
ID
Input Leakage
74F 4.75 V 0.0
I
ID
e
1.9 mA,
Test All Other Pins Grounded
I
OD
Output Leakage
74F 3.75 mA 0.0
V
IOD
e
150 mV,
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current
b
0.6 mA Max V
IN
e
0.5V
I
OS
Output Short-Circuit Current
b
60
b
150 mA Max V
OUT
e
0V
I
CC
Power Supply Current 72 mA Max
3
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AC Electrical Characteristics
74F 54F 74F
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com
Symbol Parameter V
CC
ea
5.0V C
L
e
50 pF C
L
e
50 pF
Units
C
L
e
50 pF
Min Typ Max Min Max Min Max
f
max
Maximum Clock Frequency 100 110 45 90 MHz
t
PLH
Propagation Delay 4.5 9.0 11.0 4.5 17.0 4.5 12.0
ns
t
PHL
CP to SO 5.0 9.0 12.5 5.0 14.5 5.0 13.5
AC Operating Requirements
74F 54F 74F
Symbol Parameter
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com Units
V
CC
ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 4.0 4.0 4.0 t
s
(L) SI to CP 4.0 4.0 4.0
ns
th(H) Hold Time, HIGH or LOW 4.0 4.0 4.0 t
h
(L) SI to CP 4.0 4.0 4.0
ts(H) Setup Time, HIGH or LOW 3.0 3.0 3.0 t
s
(L) Pnto CP 3.0 3.0 3.0
ns
th(H) Hold Time, HIGH or LOW 4.0 4.0 4.0 t
h
(L) Pnto CP 4.0 4.0 4.0
ts(H) Setup Time, HIGH or LOW 8.0 8.0 8.0 t
s
(L) MtoCP 8.0 8.0 8.0
ns
th(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 t
h
(L) MtoCP 2.0 2.0 2.0
ts(L) Setup Time, LOW
10.0 12.0 10.0
CS
to CP
ns
th(H) Hold Time, HIGH
10.0 10.0 10.0
CS
to CP
tw(H) CP Pulse Width 4.0 5.0 4.0
ns
t
w
(L) HIGH or LOW 6.0 9.0 6.0
4
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Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows:
74F 676 S C X
Temperature Range Family Special Variations
74F
e
Commercial QBeMilitary grade device with
54F
e
Military environmental and burn-in
processing
Device Type
Temperature Range
Package Code
C
e
Commercial (0§Ctoa70§C)
P
e
Plastic DIP
M
e
Military (b55§Ctoa125§C)
SP
e
Slim Plastic DIP
D
e
Ceramic DIP
SD
e
Slim Ceramic DIP
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
5
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6
Page 7
Physical Dimensions inches (millimeters)
28-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E28A
24-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J24A
7
Page 8
Physical Dimensions inches (millimeters) (Continued)
24-Lead (0.300×Wide) Ceramic Dual-In-Line Package (SD)
NS Package Number J24F
24-Lead (0.300×Wide) Molded Small Outline Package, JEDEC
NS Package Number M24B
8
Page 9
Physical Dimensions inches (millimeters) (Continued)
24-Lead (0.600×Wide) Molded Dual-In-Line Package (P)
NS Package Number N24A
24-Lead (0.300×Wide) Molded Dual-In-Line Package (SP)
NS Package Number N24C
9
Page 10
54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register
Physical Dimensions inches (millimeters) (Continued)
24 Lead Ceramic Flatpak (F)
NS Package Number W24C
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