Datasheet 54F533LMQB, 54F533FMQB, 54F533DMQB Datasheet (NSC)

54F/74F533
Octal Transparent Latch with TRI-STATE

Outputs

É

54F/74F533 Octal Transparent Latch with TRI-STATE Outputs

May 1995

General Description

The ’F533 consists of eight latches with TRI-STATE outputs
for bus organized system applications. The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable
(OE

) is LOW. When OE is HIGH the bus output is in the high
impedance state. The ’F533 is the same as the ’F373, ex­cept that the outputs are inverted.

Commercial Military

74F533PC N20A 20-Lead (0.300×Wide) Molded Dual-In-Line

54F533DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line

74F533SC (Note 1) M20B 20-Lead (0.300×Wide) Molded Small Outline, JEDEC

74F533SJ (Note 1) M20D 20-Lead (0.300×Wide) Molded Small Outline, EIAJ

54F533FM (Note 2) W20A 20-Lead Cerpack

54F533LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix

Package

Number

Logic Symbols

Pin Assignment

IEEE/IEC

for DIP, SOIC and Flatpak

Features

Y

Eight latches in a single package

Y

TRI-STATE outputs for bus interfacing

Y

Inverted version of the ’F373

Y

Guaranteed 4000V minimum ESD protection

Package Description

e

DMQB, FMQB and LMQB.

Connection Diagrams

Pin Assignment

for LCC

TL/F/9548– 3

TL/F/9548– 4

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/F/9548– 1

TL/F/9548

TL/F/9548– 2

Unit Loading/Fan Out

54F/74F

Pin Names Description

U.L. Input I

HIGH/LOW Output IOH/I

D0–D
LE Latch Enable Input (Active HIGH) 1.0/1.0 20 mA/
OE
O0–O

Data Inputs 1.0/1.0 20 mA/b0.6 mA

7

Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
Complementary TRI-STATE Outputs 150/40 (33.3)b3 mA/24 mA (20 mA)

7

Function Table

Inputs Output

LE OE DO

HLH L
HLL H
LLX O
XHX Z

e

H

HIGH Voltage Level

e

LOW Voltage Level

L

e

Immaterial

X

0

Functional Description

The ’F533 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
the latches are transparent, i.e., a latch output will change

inputs enters the latches. In this condition

n

state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D in-

puts a setup time preceding the HIGH-to-LOW transition of
LE. The TRI-STATE buffers are controlled by the Output
Enable (OE
bi-state mode. When OE
impedance mode but this does not interfere with entering
new data into the latches.

Logic Diagram

IH/IIL

OL

b

0.6 mA

) input. When OE is LOW, the buffers are in the

is HIGH the buffers are in the high

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

2

TL/F/9548– 5

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature

Ambient Temperature under Bias

Junction Temperature under Bias

Plastic

Pin Potential to

V

CC

Ground Pin

Input Voltage (Note 2)

Input Current (Note 2)

Voltage Applied to Output

in HIGH State (with V
Standard Output

CC

e

TRI-STATE Output

0V)

b

65§Ctoa150§C

b

55§Ctoa125§C

b

55§Ctoa175§C

b

55§Ctoa150§C

b

0.5V toa7.0V

b

0.5V toa7.0V

b

30 mA toa5.0 mA

b

0.5V to V

b

0.5V toa5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

OL

ESD Last Passing Voltage (Min) 4000V

Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol Parameter

V

V

V

V

V

I

IH

I

BVI

I

BVIT

I

CEX

V

I

OD

I

IL

I

OZH

I

OZL

I

OS

I

ZZ

I

CCZ

IH

IL

CD

OH

OL

ID

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage

Output HIGH 54F 10% V
Voltage 54F 10% V

Output LOW 54F 10% V
Voltage 74F 10% V

Input HIGH 54F 20.0
Current 74F 5.0

Input HIGH Current 54F 100
Breakdown Test 74F 7.0

Input HIGH Current 54F 1.0
Breakdown (I/O) 74F 0.5

Output HIGH 54F 250
Leakage Current 74F 50

Input Leakage
Test All Other Pins Grounded

Output Leakage
Circuit Current All Other Pins Grounded

Input LOW Current

Output Leakage Current 50 mA Max V

Output Leakage Current

Output Short-Circuit Current

Bus Drainage Test 500 mA 0.0V V

Power Supply Current 41 61 mA Max V

74F 10% V
74F 10% V
74F 5% V
74F 5% V

74F 4.75 V 0.0

74F 3.75 mA 0.0

Min Typ Max

2.5 I

CC

2.4 I

CC

2.5

CC

2.4 I

CC

2.7 I

CC

2.7 I

CC

CC

CC

b

60

CC

54F/74F

Recommended Operating
Conditions

Free Air Ambient Temperature

Military
Commercial 0

Supply Voltage

Military
Commercial

b

1.2 V Min I

0.5

0.5 I

b

0.6 mA Max V

b

50 mA Max V

b

150 mA Max V

3

Units V

mA Max V

mA Max V

mA Max V

mA Max V

V Min

V Min

CC

I

I

I

V

IN

OH

OH

OH

OH

OH

OH

OL

OL

ID

IN

IN

IN

OUT

IOD

IN

OUT

OUT

OUT

OUT

O

eb

eb

eb

eb

eb

eb

eb

e

e

e

e

e

e

e

1.9 mA

e

e

e

e

e

e

e

20 mA
24 mA

2.7V

7.0V

5.5V

0.5V

HIGH Z

b

55§Ctoa125§C

Ctoa70§C

§

a

4.5V toa5.5V

a

4.5V toa5.5V

Conditions

18 mA

1mA
3mA
1mA
3mA
1mA
3mA

V

CC

150 mV

2.7V

0.5V

0V

5.25V

AC Electrical Characteristics

74F 54F 74F

ea

T

25§C

Symbol Parameter V

A

ea

5.0V

CC

e

50 pF

C

L

e

T

A,VCC

e

C

50 pF C

L

Mil TA,V

e

Com

CC

e

50 pF

L

Units

Min Typ Max Min Max Min Max

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Propagation Delay 4.0 6.7 9.0 4.0 12.0 4.0 10.0
Dnto O

n

2.5 4.4 7.0 2.5 9.0 2.5 8.0

Propagation Delay 5.0 7.1 11.0 5.0 14.0 5.0 13.0
LE to O

n

3.0 4.7 7.0 3.0 9.0 3.0 8.0

Output Enable Time 2.0 5.9 10.0 2.0 12.5 2.0 11.0

2.0 5.6 7.5 2.0 10.5 2.0 8.5

Output Disable Time 1.5 3.4 6.5 1.5 8.5 1.5 7.0

1.5 2.7 5.5 1.5 7.5 1.5 6.5

AC Operating Requirements

74F 54F 74F

ea

25§C

T

Symbol Parameter

A

ea

CC

5.0V

V

Min Max Min Max Min Max

ts(H) Setup Time, HIGH or LOW 2.0 2.0 2.0
t

(L) Dnto LE 2.0 2.0 2.0

s

th(H) Hold Time, HIGH or LOW 3.0 3.0 3.0
t

(L) Dnto LE 3.0 3.0 3.0

h

tw(H) LE Pulse Width, HIGH 6.0 6.0 6.0 ns

T

A,VCC

e

Mil TA,V

e

Com Units

CC

ns

ns

ns

ns

ns

ns

Ordering Information

The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:

74F 533 S C X

Temperature Range Family Special Variations

e

74F

Commercial XeDevices shipped in 13×reels

e

54F

Military QBeMilitary grade device with

Device Type

Package Code

e

Plastic DIP

P

e

Ceramic DIP

D

e

Flatpak

F

e

L

Leadless Chip Carrier (LCC)

e

S

Small Outline SOIC JEDEC

e

SJ

Small Outline SOIC EIAJ

4

environmental and burn-in
processing shipped in tubes

Temperature Range

e

Commercial (0§Ctoa70§C)

C

e

Military (b55§Ctoa125§C)

M

Physical Dimensions inches (millimeters)

20-Lead Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

20-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J20A

5

Physical Dimensions inches (millimeters) (Continued)

20-Lead (0.300×Wide) Molded Small Outline Package, JEDEC (S)

20-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)

NS Package Number M20B

NS Package Number M20D

6

Physical Dimensions inches (millimeters) (Continued)

20-Lead (0.300×Wide) Molded Dual-In-Line Package (P)

NS Package Number N20A

7

Physical Dimensions inches (millimeters) (Continued)

20-Lead Ceramic Flatpak (F)

NS Package Number W20A

54F/74F533 Octal Transparent Latch with TRI-STATE Outputs

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