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TL/F/9541
54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O
January 1995
54F/74F413
64 x 4 First-In First-Out Buffer Memory with Parallel I/O
General Description
The ’F413 is an expandable fall-through type high-speed
First-In First-Out (FIFO) buffer memory organized as 64
words by four bits. The 4-bit input and output registers record and transmit, respectively, asynchronous data in parallel
form. Control pins on the input and output allow for handshaking and expansion. The 4-bit wide, 62-bit deep fallthrough stack has self-contained control logic.
Features
Y
Separate input and output clocks
Y
Parallel input and output
Y
Expandable without external logic
Y
15 MHz data rate
Y
Supply current 160 mA max
Y
Available in SOIC, (300 mil only)
Commercial Military
Package
Package Description
Number
74F413PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F413DM (Note 1) J16A 16-Lead Ceramic Dual-In-Line
Note 1: Military grade device with environmental and burn-in processing. Use suffixeDMQB.
Logic Symbol
TL/F/9541– 1
Connection Diagram
Pin Assignment
for DIP
TL/F/9541– 2
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
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Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
D0–D
3
Data Inputs 1.0/0.667 20 mA/b0.4 mA
O
0–O3
Data Outputs 50/13.3
b
1 mA/8 mA
IR Input Ready 1.0/0.667 20 mA/
b
0.4 mA
SI Shift In 1.0/0.667 20 mA/b0.4 mA
SO Shift Out 1.0/0.667 20 mA/
b
0.4 mA
OR Output Ready 1.0/0.667 20 mA/b0.4 mA
MR
Master Reset 1.0/0.667 20 mA/b0.4 mA
Functional Description
Data InputÐData is entered into the FIFO on D0–D3in-
puts. To enter data the Input Ready (IR) should be HIGH,
indicating that the first location is ready to accept data. Data
then present at the four data inputs is entered into the first
location when the Shift In (SI) is brought HIGH. An SI HIGH
signal causes the IR to go LOW. Data remains at the first
location until SI is brought LOW. When SI is brought LOW
and the FIFO is not full, IR will go HIGH, indicating that more
room is available. Simultaneously, data will propagate to the
second location and continue shifting until it reaches the
output stage or a full location. If the memory is full, IR will
remain LOW.
Data TransferÐOnce data is entered into the second cell,
the transfer of any full cell to the adjacent (downstream)
empty cell is automatic, activated by an on-chip control.
Thus data will stack up at the end of the device while empty
locations will ‘‘bubble’’ to the front. The t
PT
parameter defines the time required for the first data to travel from input
to the output of a previously empty device.
Data OutputÐData is read from the O
0–O3
outputs. When
data is shifted to the output stage, Output Ready (OR) goes
HIGH, indicating the presence of valid data. When the OR is
HIGH, data may be shifted out by bringing the Shift Out (SO)
HIGH. A HIGH signal at SO causes the OR to go LOW. Valid
data is maintained while the SO is HIGH. When SO is
brought LOW, the upstream data, provided that stage has
valid data, is shifted to the output stage. When new valid
data is shifted to the output stage, OR goes HIGH. If the
FIFO is emptied, OR stays LOW, and O
0–O3
remains as
before, i.e., data does not change if FIFO is empty.
Input Ready and Output Ready may also be used as
status signals indicating that the FIFO is completely full (Input Ready stays LOW for at least t
PT
) or completely empty
(Output Ready stays LOW for at least t
PT
).
Block Diagram
TL/F/9541– 4
2
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b
65§Ctoa150§C
Ambient Temperature under Bias
b
55§Ctoa125§C
Junction Temperature under Bias
b
55§Ctoa175§C
Plastic
b
55§Ctoa150§C
V
CC
Pin Potential to
Ground Pin
b
0.5V toa7.0V
Input Voltage (Note 2)
b
0.5V toa7.0V
Input Current (Note 2)
b
30 mA toa5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0.5V to V
CC
TRI-STATEÉOutput
b
0.5V toa5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55§Ctoa125§C
Commercial 0
§
Ctoa70§C
Supply Voltage
Military
a
4.5V toa5.5V
Commercial
a
4.5V toa5.5V
DC Electrical Characteristics
Symbol Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1.5 V Min I
IN
eb
18 mA
V
OH
Output HIGH 54F 10% V
CC
2.4 I
OH
eb
1mA
Voltage 74F 10% V
CC
2.4 V Min I
OH
eb
1mA
74F 5% V
CC
2.7 I
OH
eb
1mA
V
OL
Output LOW 54F 10% V
CC
0.5
V Min
I
OL
e
8mA
Voltage 74F 10% V
CC
0.5 I
OL
e
8mA
I
IH
Input HIGH 54F 20.0
mA Max V
IN
e
2.7V
Current 74F 5.0
I
BVI
Input HIGH Current 54F 100
mA Max V
IN
e
7.0V
Breakdown Test 74F 7.0
I
CEX
Output HIGH 54F 250
mA Max V
OUT
e
V
CC
Leakage Current 74F 50
V
ID
Input Leakage
74F 4.75 V 0.0
I
ID
e
1.9 mA
Test All Other Pins Grounded
I
OD
Output Leakage
74F 3.75 mA 0.0
V
IOD
e
150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current
b
0.4 mA Max V
IN
e
0.5V
I
OS
Output Short-Circuit Current
b
20
b
130 mA Max V
OUT
e
0V
I
CCH
Power Supply Current 115 160 mA Max V
O
e
HIGH
3
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AC Electrical Characteristics
74F 54F 74F
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com
Symbol Parameter V
CC
ea
5.0V
C
L
e
50 pF C
L
e
50 pF
Units
C
L
e
50 pF
Min Typ Max Min Max Min Max
f
max
Shift In Rate 10 8.0 10 MHz
f
max
Shift Out Rate 10 8.0 10 MHz
t
PLH
Propagation Delay 1.5 44.0 1.5 50.0 1.5 48.0
ns
t
PHL
Shift In to IR 1.5 31.0 1.5 37.0 1.5 35.0
t
PLH
Propagation Delay 1.5 52.0 1.5 57.0 1.5 55.0
ns
t
PHL
Shift Out to OR 1.5 31.0 1.5 37.0 1.5 35.0
t
PLH
Propagation Delay 1.5 46.0 1.5 52.0 1.5 50.0
ns
t
PHL
Output Data Delay 1.5 34.0 1.5 39.0 1.5 37.0
t
PLH
Propagation Delay
1.5 27.0 1.5 33.0 1.5 31.0 ns
Master Reset to IR
t
PLH
Propagation Delay
1.5 30.0 1.5 34.0 1.5 32.0 ns
Master Reset to OR
AC Operating Requirements
74F 54F 74F
Symbol Parameter
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com Units
V
CC
ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 1.0 1.0 1.0
t
s
(L) Dnto SI 1.0 1.0 1.0
ns
th(H) Hold Time, HIGH or LOW 10.0 10.0 10.0
t
h
(L) Dnto SI 10.0 10.0 10.0
tw(H) Shift In Pulse Width 5.0 5.0 5.0
t
w
(L) HIGH or LOW 10.0 10.0 10.0
ns
tw(H) Shift Out Pulse Width 7.5 8.5 7.5
t
w
(L) HIGH or LOW 10.0 10.0 10.0
tw(H) Input Ready Pulse Width,
7.5 8.5 7.5 ns
HIGH
tw(L) Output Ready Pulse Width,
5.0 5.0 5.0 ns
LOW
tw(L) Master Reset Pulse Width,
10.0 10.0 10.0 ns
LOW
t
rec
Recovery Time, MR to SI 32.0 35.0 35.0 ns
t
PT
Data Throughput Time 0.9 1.0 1.0 ms
4
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Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 413 P C X
Temperature Range Family Special Variations
74F
e
Commercial QBeMilitary grade device with
54F
e
Military environmental and burn-in
processing
Device Type
Temperature Range
Package Code
C
e
Commercial (0§Ctoa70§C)
P
e
Plastic DIP
M
e
Military (b55§Ctoa125§C)
D
e
Ceramic DIP
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
5
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54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300×Wide) Molded Dual-In-Line Package (P)
NS Package Number N16E
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failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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