Page 1
TL/F/9494
54F/74F190 Up/Down Decade Counter with Preset and Ripple Clock
November 1994
54F/74F190
Up/Down Decade Counter with Preset and Ripple Clock
General Description
The ’F190 is a reversible BCD (8421) decade counter featuring synchronous counting and asynchronous presetting.
The preset feature allows the ’F190 to be used in programmable dividers. The Count Enable input, the Terminal Count
output and the Ripple Clock output make possible a variety
of methods of implementing multistage counters. In the
counting modes, state changes are initiated by the rising
edge of the clock.
Features
Y
High-speedÐ125 MHz typical count frequency
Y
Synchronous counting
Y
Asynchronous parallel load
Y
Cascadable
Commercial Military
Package
Package Description
Number
74F190PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F190DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F190SC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC
54F190FM (Note 2) W16A 16-Lead Cerpack
54F190LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols Connection Diagrams
TL/F/9494– 1
IEEE/IEC
TL/F/9494– 4
Pin Assignment for
DIP, SOIC and Flatpak
TL/F/9494– 2
Pin Assignment
for LCC
TL/F/9494– 3
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
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Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
CE Count Enable Input (Active LOW) 1.0/3.0 20 mA/b1.8 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/
b
0.6 mA
P
0–P3
Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA
PL Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
U
/D Up/Down Count Control Input 1.0/1.0 20 mA/b0.6 mA
Q0–Q
3
Flip-Flop Outputs 50/33.3
b
1 mA/20 mA
RC
Ripple Clock Output (Active LOW) 50/33.3
b
1 mA/20 mA
TC Terminal Count Output (Active HIGH) 50/33.3
b
1 mA/20 mA
Functional Description
The ’F190 is a synchronous up/down BCD decade counter
containing four edge-triggered flip-flops, with internal gating
and steering logic to provide individual preset, count-up and
count-down operations. It has an asynchronous parallel
load capability permitting the counter to be preset to any
desired number. When the Parallel Load (PL
) input is LOW,
information present on the Parallel Data inputs (P
0–P3
)is
loaded into the counter and appears on the Q outputs. This
operation overrides the counting functions, as indicated in
the Mode Select Table. A HIGH signal on the CE
input inhib-
its counting. When CE
is LOW, internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The direction of counting is determined by
the U
/D input signal, as indicated in the Mode Select Table,
CE
and U/D can be changed with the clock in either state,
provided only that the recommended setup and hold times
are observed.
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the countdown mode or reaches 9 in the count-up mode. The TC
output will then remain HIGH until a state change occurs,
whether by counting or presetting or until U
/D is changed.
The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also
used internally to enable the Ripple Clock (RC
) output. The
RC
output is normally HIGH. When CE is LOW and TC is
HIGH, the RC
output will go LOW when the clock next goes
LOW and will stay LOW until the clock goes HIGH again.
This feature simplifies the design of multistage counters.
For a discussion and illustrations of the various methods of
implementing multistage counters, please see the ’F191
data sheet.
RC
Truth Table
Inputs Output
CE TC* CP RC
LHßß
HX X H
XL X H
*TC is generated internally
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
L
e
LOW-to-HIGH Clock Transition
ß
e
LOW Pulse
Mode Select Table
Inputs
Mode
PL CE U/D CP
HL LLCount Up
HL HLCount Down
L X X X Preset (Asyn.)
H H X X No Change (Hold)
State Diagram
TL/F/9494– 5
2
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Logic Diagram
TL/F/9494– 6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b
65§Ctoa150§C
Ambient Temperature under Bias
b
55§Ctoa125§C
Junction Temperature under Bias
b
55§Ctoa175§C
Plastic
b
55§Ctoa150§C
V
CC
Pin Potential to
Ground Pin
b
0.5V toa7.0V
Input Voltage (Note 2)
b
0.5V toa7.0V
Input Current (Note 2)
b
30 mA toa5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0.5V to V
CC
TRI-STATEÉOutput
b
0.5V toa5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55§Ctoa125§C
Commercial 0
§
Ctoa70§C
Supply Voltage
Military
a
4.5V toa5.5V
Commercial
a
4.5V toa5.5V
DC Electrical Characteristics
Symbol Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1.2 V Min I
IN
eb
18 mA
V
OH
Output HIGH 54F 10% V
CC
2.5 I
OH
eb
1mA
Voltage 74F 10% V
CC
2.5 V Min I
OH
eb
1mA
74F 5% V
CC
2.7 I
OH
eb
1mA
V
OL
Output LOW 54F 10% V
CC
0.5
V Min
I
OL
e
20 mA
Voltage 74F 10% V
CC
0.5 I
OL
e
20 mA
I
IH
Input HIGH 54F 20.0
mA Max
V
IN
e
2.7V
Current 74F 5.0
I
BVI
Input HIGH Current 54F 100
mA Max
V
IN
e
7.0V
Breakdown Test 74F 7.0
I
CEX
Output HIGH 54F 250
mA Max
V
OUT
e
V
CC
Leakage Current 74F 50
V
ID
Input Leakage
74F 4.75 V 0.0
I
ID
e
1.9 mA
Test All Other Pins Grounded
I
OD
Output Leakage
74F 3.75 mA 0.0
V
IOD
e
150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current
b
0.6
mA Max
V
IN
e
0.5V, except CE
b
1.8 V
IN
e
0.5V, CE
I
OS
Output Short-Circuit Current
b
60
b
150 mA Max V
OUT
e
0V
I
CCL
Power Supply Current 38 55 mA Max V
O
e
LOW
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AC Electrical Characteristics
74F 54F 74F
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com
Symbol Parameter V
CC
ea
5.0V
C
L
e
50 pF C
L
e
50 pF
Units
C
L
e
50 pF
Min Typ Max Min Max Min Max
f
max
Maximum Clock Frequency 100 125 75 90 MHz
t
PLH
Propagation Delay 3.0 5.5 7.5 3.0 9.5 3.0 8.5
t
PHL
CP to Q
n
5.0 8.5 11.0 5.0 13.5 5.0 12.0
ns
t
PLH
Propagation Delay 6.0 10.0 13.0 6.0 16.5 6.0 14.0
t
PHL
CP to TC 5.0 8.5 11.0 5.0 13.5 5.0 12.0
t
PLH
Propagation Delay 3.0 5.5 7.5 3.0 9.5 3.0 8.5
t
PHL
CP to RC 3.0 5.0 7.0 3.0 9.0 3.0 8.0
ns
t
PLH
Propagation Delay 3.0 5.0 7.0 3.0 9.0 3.0 8.0
t
PHL
CE to RC 3.0 5.5 7.0 3.0 9.0 3.0 8.0
t
PLH
Propagation Delay 7.0 11.0 18.0 7.0 22.0 7.0 20.0
t
PHL
U/D to RC 5.5 9.0 12.0 5.5 14.0 5.5 13.0
ns
t
PLH
Propagation Delay 4.0 7.0 10.0 4.0 13.5 4.0 11.0
t
PHL
U/D to TC 4.0 6.5 10.0 4.0 12.5 4.0 11.0
t
PLH
Propagation Delay 3.0 4.5 7.0 3.0 9.0 3.0 8.0
ns
t
PHL
Pnto Q
n
6.0 10.0 13.0 6.0 16.0 6.0 14.0
t
PLH
Propagation Delay 5.0 8.5 11.0 5.0 13.0 5.0 12.0
ns
t
PHL
PL to Q
n
5.5 9.0 12.0 5.5 14.5 5.5 13.0
AC Operating Requirements
74F 54F 74F
Symbol Parameter
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com Units
V
CC
ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 4.5 6.0 5.0
t
s
(L) Pnto PL 4.5 6.0 5.0
ns
th(H) Hold Time, HIGH or LOW 2.0 2.0 2.0
t
h
(L) Pnto PL 2.0 2.0 2.0
ts(L) Setup Time, LOW
10.0 10.5 10.0
CE
to CP
ns
th(L) Hold Time, LOW
000
CE
to CP
ts(H) Setup Time, HIGH or LOW 12.0 12.0 12.0
t
s
(L) U/D to CP 12.0 12.0 12.0
ns
th(H) Hold Time, HIGH or LOW 0 0 0
t
h
(L) U/D to CP 0 0 0
tw(L) PL Pulse Width, LOW 6.0 8.5 6.0 ns
tw(L) CP Pulse Width, LOW 5.0 7.0 5.0 ns
t
rec
Recovery Time PL to CP 6.0 7.5 6.0 ns
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Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 190 S C X
Temperature Range Family Special Variations
74F
e
Commercial XeDevices shipped in 13×reels
54F
e
Military QBeMilitary grade device with
environmental and burn-in
Device Type
processing shipped in tubes
Package Code
Temperature Range
P
e
Plastic DIP
C
e
Commercial (0§Ctoa70§C)
D
e
Ceramic DIP
M
e
Military (b55§Ctoa125§C)
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
6
Page 7
7
Page 8
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
8
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Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.150×Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M16A
16-Lead (0.300×Wide) Molded Dual-In-Line Package (P)
NS Package Number N16E
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54F/74F190 Up/Down Decade Counter with Preset and Ripple Clock
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
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with instructions for use provided in the labeling, can effectiveness.
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