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54ACTQ574
Quiet Series Octal D Flip-Flop with TRI-STATE
®
Outputs
54ACTQ574 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs
August 1998
General Description
The ACTQ574 is a high-speed, low-power octal D-type
flip-flop with a buffered Common Clock (CP) and a buffered
common Output Enable (OE). The information presented to
the D inputs is stored in the flip-flops on the LOW-to-HIGH
clock (CP) transition.
ACTQ574 utilizes Quiet Series technology to guarantee
quiet output switching and improve dynamic threshold performance. FACTQuiet Series
™
features GTO™output control and undershoot corrector in addition to a split ground bus
for superior performance.
The ACTQ574 is functionally identical to the ’ACTQ374 but
with different pin-out.
Logic Diagrams
DS100243-1
Features
n ICCand IOZreduced by 50
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Inputs and outputs on opposite sides of the package
allowing easy interface with microprocessors
n Functionally identical to the ACTQ374
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Outputs source/sink 24 mA
n Faster prop delays than the standard ACT574
n 4 kV minimum ESD immunity
%
IEEE/IEC
DS100243-2
Pin Names Description
D
0–D7
Data Inputs
CP Clock Pulse Input
OE
O
0–O7
GTO™is a trademark of National Semiconductor Corporation.
®
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
®
FACT
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
© 1998 National Semiconductor Corporation DS100243 www.national.com
™
is a trademark of Fairchild Semiconductor Corporation.
TRI-STATE Output Enable Input
TRI-STATE Outputs
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Connection Diagrams Functional Description
Pin Assignment
for DIP and Flatpak
TheACTQ574 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
go to the high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Function Table
Inputs Internal Outputs Function
DS100243-3
CP D Q O
H H L NC Z Hold
N
OE
H H H NC Z Hold
Pin Assignment for LCC
H
H
L
L
L L Z Load
N
H H Z Load
N
L L L Data Available
N
H H H Data Available
N
L H L NC NC No Change in
L H H NC NC No Change in
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
DS100243-4
Z=High Impedance
=
N
LOW-to-HIGH Transition
NC=No Change
Logic Diagram
Data
Data
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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DS100243-5
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Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DC Input Diode Current (I
=
−0.5V −20 mA
V
I
=
V
V
I
CC
DC Input Voltage (V
DC Output Diode Current (I
=
−0.5V −20 mA
V
O
=
V
V
O
CC
DC Output Voltage (V
DC Output Source
or Sink Current (I
or Ground Current
DC V
CC
per Output Pin (I
Storage Temperature (T
DC Latch-Up Source or
Sink Current
Junction Temperature (T
) −0.5V to +7.0V
CC
)
IK
+ 0.5V +20 mA
) −0.5V to VCC+ 0.5V
I
)
OK
+ 0.5V +20 mA
) −0.5V to VCC+ 0.5V
O
)
O
or I
CC
)
GND
) −65˚C to +150˚C
STG
)
J
±
50 mA
±
50 mA
±
300 mA
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
’ACTQ 4.5V to 5.5V
Input Voltage (V
Output Voltage (VO) 0VtoV
Operating Temperature (TA)
54ACTQ −55˚C to +125˚C
Minimum Input Edge Rate ∆V/∆t
’ACTQ Devices
from 0.8V to 2.0V
V
IN
@
V
CC
Note 1: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C.
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
) 0VtoV
I
4.5V, 5.5V 125 mV/ns
™
DC Electrical Characteristics for ’ACTQ Family Devices
54ACTQ
Symbol Parameter V
V
IH
Minimum High Level 4.5 2.0 V V
Input Voltage 5.5 2.0 or V
V
IL
Maximum Low Level 4.5 0.8 V V
Input Voltage 5.5 0.8 or V
V
OH
Minimum High Level 4.5 4.4 V I
Output Voltage 5.5 5.4
V
OL
Maximum Low Level 4.5 0.1 V I
Output Voltage 5.5 0.1
I
IN
I
OZ
Maximum Input Leakage Current 5.5
Maximum TRI-STATE 5.5
Leakage Current V
I
CCT
I
OLD
Maximum ICC/Input 5.5 1.6 mA V
(Note 4) 5.5 50 mA V
Minimum Dynamic
I
I
OHD
CC
Output Current 5.5 −50 mA V
Maximum Quiescent 5.5 80.0 µA V
Supply Current or GND (Note 5)
CC
(V) −55˚C to +125˚C
Guaranteed Limits
4.5 3.70 V I
5.5 4.70 I
4.5 0.50 V I
5.5 0.50 I
=
T
A
±
1.0 µA V
±
5.0 µA V
circuits outside databook specifications.
Units Conditions
=
0.1V
OUT
− 0.1V
CC
=
0.1V
OUT
− 0.1V
CC
=
−50 µA
OUT
(Note 3)
=
V
OH
OH
OUT
IN
V
=
−24 mA
=
−24 mA
=
or V
IL
50 µA
(Note 3)
=
V
OL
OL
IN
I
I
O
I
OLD
OHD
IN
=
=
=
=
=
V
V
=
V
=
V
24 mA
24 mA
CC
IL,VIH
V
CC
CC
=
=
V
or V
IL
, GND
, GND
− 2.1V
1.65V Max
3.85V Min
CC
CC
CC
IH
IH
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DC Electrical Characteristics for ’ACTQ Family Devices (Continued)
54ACTQ
Symbol Parameter V
CC
=
T
A
Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
V
OLP
V
OLV
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I
Note 6: Plastic DIP package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output
Note 8: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (V
f=1 MHz.
Quiet Output 5.0 1.5 V (Notes 6, 7)
Maximum Dynamic V
OL
Quiet Output 5.0 −1.2 V (Notes 6, 7)
Minimum Dynamic V
for 54ACTQ@25˚C is identical to 74ACTQ@25˚C.
CC
OL
@
GND.
), 0V to threshold (V
ILD
AC Electrical Characteristics
54ACTQ
V
CC
Symbol Parameter (V) to +125˚C Units
(Note 9) C
f
max
t
, Propagation Delay 5.0 1.0 11.0 ns
PLH
t
PHL
t
, Output Enable Time 5.0 1.0 11.0 ns
PZH
t
PZL
t
, Output Disable Time 5.0 1.0 10.0 ns
PHZ
t
PLZ
Note 9: Voltage Range 5.0 is 5.0V±0.5V.
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
Maximum Clock
Frequency
CP to O
n
5.0 95 MHz
) or LOW to HIGH (t
OSHL
=
T
−55˚C
A
=
50 pF
L
Min Max
). Parameter guaranteed by design.
OSLH
),
IHD
AC Operating Requirements
54ACTQ
V
CC
Symbol Parameter (V) to +125˚C Units
(Note 11) C
t
S
t
H
t
W
Setup Time, HIGH or LOW 5.0 3.5 ns
D
to CP
n
Hold Time, HIGH or LOW 5.0 2.0 ns
D
to CP
n
CP Pulse Width, 5.0 5.0 ns
HIGH or LOW
Note 11: Voltage Range 5.0 is 5.0V±0.5V
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=
T
−55˚C
A
=
50 pF
L
Guaranteed Minimum
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Capacitance
Symbol Parameter Typ Units Conditions
C
IN
C
PD
Input Capacitance 4.5 pF V
Power Dissipation Capacitance 40.0 pF V
=
CC
=
CC
OPEN
5.0V
5 www.national.com
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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Page 7
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Integrated Circuit (S)
NS Package Number M20B
20-Lead Plastic Dual-In-LIne Package (P)
NS Package Number N20B
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Page 8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
54ACTQ574 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs
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