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54ACTQ544
Quiet Series Octal Registered Transceiver with
TRI-STATE
®
Outputs
General Description
The ACTQ544 is an inverting octal transceiver containing
two sets of D-type registers for temporary storage of data
flowing in either direction. Separate Latch Enable and Output Enable inputsare provided for each register to permit independent input and output control in either direction of data
flow. The ’544 inverts data in both directions.
The ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series
™
features GTO™output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Features
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n 8-bit inverting octal latched transceiver
n Separate controls for data flow in each direction
n Back-to-back registers for storage
n Outputs source/sink 24 mA
n 4 kV minimum ESD immunity
Logic Symbols
Pin Names Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
CEAB
A-to-B Enable Input (Active LOW)
CEBA
B-to-A Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input (Active LOW)
LEBA
B-to-A Latch Enable Input (Active LOW)
A
0–A7
A-to-B Data Inputs or
B-to-A TRI-STATE Outputs
B
0–B7
B-to-A Data Inputs or
A-to-B TRI-STATE Outputs
GTO™is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
™
is a trademark of Fairchild Semiconductor Corporation.
DS100248-1
IEEE/IEC
DS100248-4
August 1998
54ACTQ544 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100248 www.national.com
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Connection Diagrams
Functional Description
TheACTQ544 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input
must be LOW in order to enter data from A0–A7or take data
from B0–B7, as indicated in the Data I/O Control Table.With
CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A
latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both LOW,
the TRI-STATE B output buffers are active and reflect the
data present at the output of the A latches. Control of data
flow from B to A is similar, but using the CEBA, LEBA and
OEBA inputs.
Data I/O Control Table
Inputs Latch Output
CEAB
LEAB OEAB Status Buffers
H X X Latched High Z
X H X Latched —
L L X Transparent —
X X H — High Z
L X L — Driving
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Pin Assignment for
DIP and Flatpak
DS100248-2
Pin Assignment
for LCC
DS100248-3
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Logic Diagram
DS100248-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+ 0.5V
DC Output Source
or Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
±
50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
DC Latch-up Source or
Sink Current
±
300 mA
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage V
CC
’ACTQ 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA) (Note 2)
54ACTQ −55˚C to +125˚C
Minimum Input Edge Rate ∆V/∆t
’ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
®
circuits outside databook specifications.
Note 2: Surface mount and plastic dip packaging is not recommended for
applications requiring greater than 2000 temperature cycles from −40˚C to
+125˚C.
DC Characteristics for ’ACTQ Family Devices
54ACTQ
Symbol Parameter V
CC
T
A
=
Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
V
IH
Minimum High Level 4.5 2.0 V V
OUT
=
0.1V
Input Voltage 5.5 2.0 or V
CC
− 0.1V
V
IL
Maximum Low Level 4.5 0.8 V V
OUT
=
0.1V
Input Voltage 5.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High Level 4.5 4.4 V I
OUT
=
−50 µA
Output Voltage 5.5 5.4
(Note 3)
V
IN
=
V
IL
or V
IH
4.5 3.70 V I
OH
=
−24 mA
5.5 4.70 I
OH
=
−24 mA
V
OL
Maximum Low Level 4.5 0.1 V I
OUT
=
50 µA
Output Voltage 5.5 0.1
(Note 3)
V
IN
=
V
IL
or V
IH
4.5 0.50 V I
OL
=
24 mA
5.5 0.50 I
OL
=
24 mA
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
I
OZT
Maximum I/O 5.5
±
10.0 µA VI, (OE)=VIL,V
IH
Leakage Current V
O
=
V
CC
, GND
I
CCT
Maximum 5.5 1.6 mA V
I
=
V
CC
− 2.1V
I
CC
/Input
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DC Characteristics for ’ACTQ Family Devices (Continued)
54ACTQ
Symbol Parameter V
CC
T
A
=
Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
I
OLD
Minimum Dynamic
Output Current (Note 4)
5.5 50 mA V
OLD
=
1.65V Max
I
OHD
5.5 −50 mA V
OHD
=
3.85V Min
I
CC
Maximum Quiescent 5.5 160.0 µA V
IN
=
V
CC
Supply Current or GND (Note 5)
V
OLP
Quiet Output 5.0 1.6 V 2–12, 13
Maximum Dynamic V
OL
(Notes 6, 7)
V
OLV
Quiet Output 5.0 −1.2 V 2–12, 13
Minimum Dynamic V
OL
(Notes 6, 7)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I
CC
for 54ACTQ@25˚C is identical to 74ACTQ@25˚C.
Note 6: Plastic DIP package.
Note 7: Max number of outputs defined as (n-1). Data Inputs are driven 0V to 3V, one output
@
GND.
Note 8: Max number of Data Inputs (n) switching (n-1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f=1 MHz.
AC Electrical Characteristics
54ACTQ
V
CC
T
A
=
−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 9) C
L
=
50 pF
Min Max
t
PLH
Propagation Delay
t
PHL
Transparent Mode 5.0 2.0 9.5 ns
A
n
to Bnor Bnto A
n
t
PLH
Propagation Delay 5.0 2.0 11.0 ns
t
PHL
LEBA, LEAB to An,B
n
t
PZH
Output Enable Time
t
PZL
OEBA or OEAB to Anor B
n
5.0 1.5 13.0 ns
CEBA or CEAB to A
n
or B
n
t
PHZ
Output Disable Time
t
PLZ
OEBA or OEAB to Anor B
n
5.0 1.5 9.0 ns
CEBA or CEAB to A
n
or B
n
Note 9: Voltage Range 5.0 is 5.0V±0.5V
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by design. Not
tested.
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AC Operating Requirements
54ACTQ
V
CC
T
A
=
−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 11) C
L
=
50 pF
Guaranteed
Minimum
t
s
Setup Time, HIGH or LOW 5.0 3.0 ns
A
n
or Bnto LEBA or LEAB
t
h
Hold Time, HIGH or LOW 5.0 1.5 ns
A
n
or Bnto LEBA or LEAB
t
w
Latch Enable, B to A 5.0 4.0 ns
Pulse Width, LOW
Note 11: Voltage Range 5.0 is 5.0V±0.5V
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
=
5.0V
C
PD
Power Dissipation 80.0 pF V
CC
=
5.0V
Capacitance
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Physical Dimensions inches (millimeters) unless otherwise noted
28-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E28A
24-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J24F
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
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Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
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Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: sea.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
24-Lead Ceramic Flatpak (F)
NS Package Number W24C
54ACTQ544 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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