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54ACT899
9-Bit Latchable Transceiver with Parity
Generator/Checker
General Description
The ACT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through
transceiver orit can generate/check parity from the 8-bit data
busses in either direction. TheACT899 features independent
latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error
signal output pins for checking parity.
Features
n Latchable transceiver with output sink of 24 mA
n Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
n Independent latch enable for A-to-B and B-to-A
directions
n Select pin for ODD/EVEN parity
n ERRA and ERRB output pins for parity checking
n Ability to simultaneously generate and check parity
n May be used in system applications in place of the ’280
n May be used in system applications in place of the ’657
and ’373 (no need to change T/R to check parity)
n 4 kV minimum ESD immunity
n Standard Microcircuit Drawing (SMD) 5962-9314101
Logic Symbol
Connection Diagram
Pin Names Description
A
0–A7
A Bus Data Inputs/Data Outputs
B
0–B7
B Bus Data Inputs/Data Outputs
APAR, BPAR A and B Bus Parity Inputs
ODD/EVEN
ODD/EVEN Parity Select, Active LOW
for EVEN Parity
GBA, GAB
Output Enables for A or B Bus, Active
LOW
SEL
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
LEA, LEB Latch Enables for A and B Latches,
HIGH for Transparent Mode
ERRA, ERRB
Error Signals for Checking Generated
Parity with Parity In, LOW if Error
Occurs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100245-1
Pin Assignment for LCC
DS100245-2
August 1998
54ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker
© 1998 National Semiconductor Corporation DS100245 www.national.com
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Functional Description
The ACT899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
•
BusA (B) communicates to Bus B (A), parity is generated
and passed on to the B (A) Bus as BPAR (APAR).If LEB
(LEA) is HIGH and the Mode Select (SEL) is LOW, the
parity generated from B[0:7] (A[0:7]) can be checked and
monitored by ERRB (ERRA).
•
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit error to the CPU).
•
Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function Table
below).
Function Table
Inputs Operation
GAB
GBA SEL LEA LEB
H H X X X Busses A and B are TRI-STATE
®
.
H L L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity
→
APAR. Generated parity checked against BPAR and output as
ERRB.
H L L H H Generates parity from B[0:7] based on O/E. Generated parity
→
APAR. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check
as ERRA.
H L L X L Generates parity from B latch data based on O/E. Generated parity
→
APAR. Generated parity checked against latched BPAR and output as
ERRB.
H L H X H BPAR/B[0:7]→APAR/A0:7] Feed-through mode. Generated parity
checked against BPAR and output as ERRB.
H L H H H BPAR/B[0:7]→APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch
for generate/check as ERRA.
L HLHLGenerates parity for A[0:7] based on O/E. Generated parity→BPAR.
Generated parity checked against APAR and output as ERRA.
L H L H H Generates parity from A[0:7] based on O/E. Generated parity
→
BPAR. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check
as ERRB.
L H L L X Generates parity from A latch data based on O/E. Generated parity
→
BPAR. Generated parity checked against latched APAR and output as
ERRA.
L H H H L APAR/A[0:7]→BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and
output as ERRA.
L HHHHAPAR/A[0:7]→BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch
for generate/check as ERRB.
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Note 1: O/E=ODD/EVEN
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Functional Block Diagram
AC Path
DS100245-3
DS100245-4
An,APAR→Bn,BPAR
(B
n
,BPAR→An, APAR)
FIGURE 1.
DS100245-5
A
n
→
BPAR
(B
n
→
APAR)
FIGURE 2.
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AC Path (Continued)
DS100245-6
A
n
→
ERRA
(B
n
→
ERRB)
FIGURE 3.
DS100245-7
O/E→ERRA
O/E→ERRB
FIGURE 4.
DS100245-8
O/E→BPAR
(O/E→APAR)
FIGURE 5.
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AC Path (Continued)
DS100245-9
APAR→ERRA
(BPAR→ERRB)
FIGURE 6.
DS100245-10
ZH, HZ
FIGURE 7.
DS100245-11
ZL, LZ
FIGURE 8.
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AC Path (Continued)
DS100245-12
SEL→BPAR
(SEL→APAR)
FIGURE 9.
DS100245-13
LEA→BPAR, B[0:7]
(LEB→APAR,A[0:7])
FIGURE 10.
DS100245-14
TS(H), TH(H)
LEA→APAR,A[0:7]
(LEB→BPAR, B[0:7])
FIGURE 11.
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AC Path (Continued)
DS100245-15
TS(L), TH(L)
LEA→APAR,A[0:7]
(LEB→BPAR, B[0:7])
FIGURE 12.
DS100245-16
FIGURE 13.
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Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+ 0.5V
DC Output Source
or Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
±
50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
DC Latch-Up Source or
Sink Current
±
300 mA
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
’ACT 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA)
54ACT −55˚C to +125˚C
Minimum Input Edge Rate ∆V/∆t
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V 125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
®
circuits outside databook specifications.
Note 3: PLCC packaging is not recommended for applications requiring
greater than 2000 temperature cycles from −40˚C to +125˚C.
DC Electrical Characteristics for ’ACT Family Devices
54ACT
Symbol Parameter V
CC
T
A
=
Units Conditions
(V) −55˚C to +125˚C
Guaranteed
Limits
V
IH
Minimum High Level 4.5 2.0 V V
OUT
=
0.1V
Input Voltage 5.5 2.0 or V
CC
− 0.1V
V
IL
Maximum Low Level 4.5 0.8 V V
OUT
=
0.1V
Input Voltage 5.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High Level 4.5 4.4 V I
OUT
=
−50 µA
Output Voltage 5.5 5.4
(Note 4)
V
IN
=
V
IL
or V
IH
4.5 3.70 V IOH= −24 mA
5.5 4.70 I
OH
= −24 mA
V
OL
Maximum Low Level 4.5 0.1 V I
OUT
=
50 µA
Output Voltage 5.5 0.1
(Note 4)
V
IN
=
V
IL
or V
IH
4.5 0.50 V IOL=24mA
5.5 0.50 I
OL
=24mA
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
I
OZ
Maximum TRI-STATE 5.5
±
10.0 µA V
I
=
V
IL,VIH
Leakage Current V
O
=
V
CC
, GND
I
CCT
Maximum ICC/Input 5.5 1.6 mA V
I
=
V
CC
− 2.1V
I
OLD
Minimum Dynamic
Output Current (Note 5)
5.5 50 mA V
OLD
=
1.65V Max
I
OHD
5.5 −50 mA V
OHD
=
3.85V Min
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DC Electrical Characteristics for ’ACT Family Devices (Continued)
54ACT
Symbol Parameter V
CC
T
A
=
Units Conditions
(V) −55˚C to +125˚C
Guaranteed
Limits
I
CC
Maximum Quiescent 5.5 160.0 µA V
IN
=
V
CC
Supply Current or GND (Note 6)
Note 4: Maximum of 9 outputs loaded; thresholds on input associated with output under test.
Note 5: Maximum test duration 2.0 ms, one output loaded at a time.
Note 6: I
CC
for 54ACT@25˚C is identical to 74ACT@25˚C.
AC Electrical Characteristics
54ACT
V
CC
T
A
=
−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 7) C
L
=
50 pF
Min Max
t
PLH
Propagation Delay 5.0 1.5 13.5 ns
Figure 1
t
PHL
An,Bnto Bn,A
n
t
PLH
Propagation Delay 5.0 1.5 11.0 ns
Figure 1
t
PHL
APAR, BPAR to BPAR, APAR
t
PLH
Propagation Delay 5.0 1.5 16.0 ns
Figure 2
t
PHL
An,Bnto BPAR, APAR
t
PLH
Propagation Delay 5.0 1.5 16.0 ns
Figure 3
t
PHL
An,Bnto ERRA, ERRB
t
PLH
Propagation Delay 5.0 1.5 16.0 ns
Figure 4
t
PHL
ODD/EVEN to ERRA, ERRB
t
PLH
Propagation Delay 5.0 1.5 14.5 ns
Figure 5
t
PHL
ODD/EVEN to APAR, BPAR
t
PLH
Propagation Delay 5.0 1.5 11.5 ns
Figure 6
t
PHL
APAR, BPAR to ERRA, ERRB
t
PLH
Propagation Delay 5.0 1.5 12.5 ns
Figure 9
t
PHL
SEL to APAR, BPAR
t
PLH
Propagation Delay 5.0 1.5 13.5 ns
Figures 10, 11
t
PHL
LEB to An,B
n
t
PLH
Propagation Delay 5.0 1.5 16.0 ns
Figures 10, 11
t
PHL
LEA to APAR, BPAR
t
PLH
Propagation Delay 5.0 1.5 16.0 ns
Figure 12
t
PHL
LEA, LEB to ERRA, ERRB
t
PZH
Output Enable Time 5.0 1.5 16.0 ns
Figures 7, 8
t
PZL
GBA or GAB to An,B
n
t
PZH
Output Enable Time 5.0 1.5 11.0 ns
Figures 7, 8
t
PZL
GBA or GAB to BPAR or APAR
t
PHZ
Output Disable Time 5.0 1.5 11.0 ns
Figures 7, 8
t
PHL
GBA or GAB to An,B
n
t
PHZ
Output Disable Time 5.0 1.5 11.0 ns
Figures 7, 8
t
PLZ
GBA or GAB to BPAR, APAR
Note 7: Voltage Range 5.0 is 5.0V±0.5V.
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AC Operating Requirements
54ACT
V
CC
T
A
=
−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 8) C
L
=
50 pF
Guaranteed
Minimum
t
s
Setup Time, HIGH or LOW 5.0 3.0 ns
Figures
11, 12
An,Bn, PAR to LEA, LEB
t
h
Hold Time, HIGH or LOW 5.0 3.0 ns
Figures
11, 12
An,Bn, PAR to LEA, LEB
t
w
Pulse Width for LEB, LEA 5.0 4.0 ns
Figure 13
Note 8: Voltage Range 5.0=5.0V±0.5V.
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
=
5.0V
C
PD
Power Dissipation 210 pF V
CC
=
5.0V
Capacitance
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Physical Dimensions inches (millimeters) unless otherwise noted
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with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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28-Lead Plastic Chip Carrier (Q)
NS Package Number E28A
28-Lead Plastic Chip Carrier (Q)
NS Package Number J28A
54ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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