Datasheet 5962-8755601SA, 5962-8755601RA, 5962-87556012A, 54ACT373FM-MLS, 54ACT373DM-MLS Datasheet (NSC)

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54AC373•54ACT373 Octal Transparent Latch with TRI-STATE

Outputs

General Description

The ’AC/’ACT373 consists of eight latches with TRI-STATE outputs forbus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE isHIGH, the bus outputis in the high impedance state.

Features

n ICCand IOZreduced by 50

n Eight latches in a single package n TRI-STATE outputs for bus interfacing n Outputs source/sink 24 mA n ’ACT373 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD)

— ’AC373: 5962-87555 — ’ACT373: 5962-87556

Logic Symbols

Pin Names Description

0–D7

Data Inputs LE Latch Enable Input OE

Output Enable Input O

0–O7

TRI-STATE Latch Outputs

TRI-STATE®is a registered trademark of National Semiconductor Corporation. FACT

is a registered trademark of Fairchild Semiconductor Corporation.

DS100329-1

IEEE/IEC

DS100329-2

August 1998

54AC373

•

54ACT373 Octal Transparent Latch with TRI-STATE Outputs

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Connection Diagrams

Functional Description

The ’AC/’ACT373 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the D

inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATEstandard outputs are controlled by the Output Enable (OE)input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Truth Table

Inputs Outputs

LE OE

XHX Z HLL L HLH H LLX O

HIGH Voltage Level L=LOW Voltage Level Z=High Impedance X=Immaterial O

Previous O

before HIGH to Low transition of Latch Enable

Pin Assignment for DIP

and Flatpak

DS100329-3

Pin Assignment for LCC

DS100329-4

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Logic Diagram

DS100329-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V

) −0.5V to +7.0V

DC Input Diode Current (I

)

−0.5V −20 mA

+ 0.5V +20 mA

DC Input Voltage (V

) −0.5V to VCC+ 0.5V

DC Output Diode Current (I

)

−0.5V −20 mA

+ 0.5V +20 mA

DC Output Voltage (V

) −0.5V to VCC+ 0.5V

DC Output Source

or Sink Current (I

)

50 mA

DC V

or Ground Current

per Output Pin (I

or I

GND

)

50 mA

Storage Temperature (T

STG

) −65˚C to +150˚C

Junction Temperature (T

)

CDIP 175˚C

Recommended Operating Conditions

Supply Voltage (VCC)

’AC 2.0V to 6.0V ’ACT 4.5V to 5.5V

Input Voltage (V

) 0VtoV

Output Voltage (VO) 0VtoV

Operating Temperature (TA)

54AC/ACT −55˚C to +125˚C

Minimum Input Edge Rate (∆V/∆t)

’AC Devices V

from 30%to 70%of V

3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

’ACT Devices V

from 0.8V to 2.0V

4.5V, 5.5V 125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT

circuits outside databook specifications.

DC Characteristics for ’AC Family Devices

54AC

Symbol Parameter V

Units Conditions

(V) −55˚C to +125˚C

Guaranteed Limits

Minimum High 3.0 2.1 V

OUT

0.1V

Level Input 4.5 3.15 V or V

− 0.1V

Voltage 5.5 3.85

Maximum Low 3.0 0.9 V

OUT

0.1V

Level Input 4.5 1.35 V or V

− 0.1V

Voltage 5.5 1.65

Minimum High 3.0 2.9 I

OUT

−50 µA Level Output 4.5 4.4 V Voltage 5.5 5.4

(Note 2) V

or V

3.0 2.4 −12 mA

4.5 3.7 V I

−24 mA

5.5 4.7 −24 mA

Maximum Low 3.0 0.1 I

OUT

50 µA Level Output 4.5 0.1 V Voltage 5.5 0.1

(Note 2) V

or V

3.0 0.50 12 mA

4.5 0.50 V I

24 mA

5.5 0.50 24 mA

Maximum Input 5.5

1.0 µA V

, GND

Leakage Current

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DC Characteristics for ’AC Family Devices (Continued)

54AC

Symbol Parameter V

Units Conditions

(V) −55˚C to +125˚C

Guaranteed Limits

Maximum VI(OE)=VIL,V

TRI-STATE 5.5

5.0 µA V

, GND

Current V

, GND

OLD

(Note 3) Minimum Dynamic Output Current

5.5 50 mA V

OLD

1.65V Max

OHD

5.5 −50 mA V

OHD

3.85V Min

Maximum Quiescent 5.5 80.0 µA V

Supply Current or GND

Note 2: All outputs loaded, thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: I

and I

3.0V are guaranteed to be less than or equal to the respective limit@5.5V VCC.

for 54AC@25˚C is identical to 74AC@25˚C.

DC Characteristics for ’ACT Family Devices

54ACT

Symbol Parameter V

Units Conditions

(V) −55˚C to +125˚C

Guaranteed Limits

Minimum High Level 4.5 2.0 V V

OUT

0.1V

Input Voltage 5.5 2.0 or V

− 0.1V

Maximum Low Level 4.5 0.8 V V

OUT

0.1V

Input Voltage 5.5 0.8 or V

− 0.1V

Minimum High Level 4.5 4.4 V I

OUT

−50 µA

Output Voltage 5.5 5.4

(Note 5) V

or V

4.5 3.70 V I

−24 mA

5.5 4.70 −24 mA

Maximum Low Level 4.5 0.1 V I

OUT

50 µA

Output Voltage 5.5 0.1

(Note 5) V

or V

4.5 0.50 V I

24 mA

5.5 0.50 24 mA

Maximum Input Leakage Current

5.5

1.0 µA V

, GND

Maximum TRI-STATE 5.5

5.0 µA V

IL,VIH

Current V

, GND

CCT

Maximum ICC/Input 5.5 1.6 mA V

− 2.1V

OLD

(Note 6) Minimum Dynamic 5.5 50 mA V

OLD

1.65V Max

OHD

Output Current 5.5 −50 mA V

OHD

3.85V Min

Maximum Quiescent 5.5 80.0 µA V

Supply Current or GND

Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: I

for 54ACT@25˚C is identical to 74ACT@25˚C.

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AC Electrical Characteristics

54AC

−55˚C

Symbol Parameter (V) to +125˚C Units

(Note 8) C

50 pF

Min Max

PLH

Propagation Delay 3.3 1.0 16.5 ns D

to O

5.0 1.5 11.5

PHL

Propagation Delay 3.3 1.0 16.0 ns D

to O

5.0 1.5 11.5

PLH

Propagation Delay 3.3 1.0 16.5 ns LE to O

5.0 1.5 12.0

PHL

Propagation Delay 3.3 1.0 15.0 ns LE to O

5.0 1.5 11.0

PZH

Output Enable Time 3.3 1.0 14.0 ns

5.0 1.5 10.5

PZL

Output Enable Time 3.3 1.0 13.5 ns

5.0 1.5 10.0

PHZ

Output Disable Time 3.3 1.0 16.0 ns

5.0 1.5 13.5

PLZ

Output Disable Time 3.3 1.0 13.0 ns

5.0 1.5 10.5

Note 8: Voltage Range 3.3 is 3.3V±0.3V

Voltage Range 5.0 is 5.0V

0.5V

AC Operating Requirements

54AC

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 9) C

50 pF

Guaranteed Minimum

Setup Time, HIGH or LOW 3.3 6.5 ns D

to LE 5.0 5.0

Hold Time, HIGH or LOW 3.3 1.0 ns D

to LE 5.0 1.0

LE Pulse Width, 3.3 6.5 ns HIGH 5.0 5.0

Note 9: Voltage Range 3.3 is 3.3V±0.3V

Voltage Range 5.0 is 5.0V

0.5V

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AC Electrical Characteristics

54ACT

−55˚C

Symbol Parameter (V) to +125˚C Units

(Note 10) C

50 pF

Min Max

PLH

Propagation Delay 5.0 1.5 12.5 ns D

to O

PHL

Propagation Delay 5.0 1.5 12.5 ns D

to O

PLH

Propagation Delay 5.0 1.5 12.5 ns LE to O

PHL

Propagation Delay 5.0 1.5 11.5 ns LE to O

PZH

Output Enable Time 5.0 1.5 11.5 ns

PZL

Output Enable Time 5.0 1.5 11.0 ns

PHZ

Output Disable Time 5.0 1.5 14.0 ns

PLZ

Output Disable Time 5.0 1.5 11.0 ns

Note 10: Voltage Range 5.0 is 5.0V±0.5V

AC Operating Requirements

54ACT

−55˚C

Symbol Parameter (V) to +125˚C Units

(Note 11) C

50 pF

Guaranteed

Minimum

Setup Time, HIGH or LOW 5.0 8.5 ns D

to LE

Hold Time, HIGH or LOW 5.0 1.0 ns D

to LE

LE Pulse Width, HIGH 5.0 8.5 ns

Note 11: Voltage Range 5.0 is 5.0V±0.5V

Capacitance

Symbol Parameter Typ Units Conditions

Input Capacitance 4.5 pF V

OPEN

Power Dissipation Capacitance 40.0 pF V

5.0V

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Physical Dimensions inches (millimeters) unless otherwise noted

20 Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

20 Lead Ceramic Dual-In-Line Package (D)

NS Package Number J20A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustainlife, and whosefailure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expectedto result in a significant injury to the user.

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause thefailure of the life support device or system,or to affect its safety or effectiveness.

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20-Lead Ceramic Flatpak (F)

NS Package Number W20A

54AC373

•

54ACT373 Octal Transparent Latch with TRI-STATE Outputs

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.