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54AC299•54ACT299
8-Input Universal Shift/Storage Register with Common
Parallel I/O Pins
General Description
The ’AC/’ACT299 is an 8-bit universal shift/storage register
with TRI-STATE
®
outputs. Four modes of operation are possible: hold (store), shiftleft,shiftrightand load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs
are provided for flip-flops Q
0,Q7
to allow easy serial cascading.A separate active LOW Master Reset is used to reset the
register.
Features
n ICCand IOZreduced by 50
%
n Common parallel I/O for reduced pin count
n Additional serial inputs and outputs for expansion
n Four operating modes: shift left, shift right, load and
store
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n ’ACT299 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
’AC299: 5962-88754
’ACT299: 5962-88771
Ordering Code:
Logic Symbols Connection Diagrams
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100252-1
IEEE/IEC
DS100252-4
Pin Assignment
for DIP and Flatpak
DS100252-2
Pin Assignment for LCC
DS100252-3
September 1998
54ACC299
•
54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
© 1998 National Semiconductor Corporation DS100252 www.national.com
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Connection Diagrams (Continued)
Pin Names Description
CP Clock Pulse Input
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S
0,S1
Mode Select Inputs
MR
Asynchronous Master Reset
OE
1
,OE
2
TRI-STATE Output Enable Inputs
I/O
0
–I/O
7
Parallel Data Inputs or
TRI-STATE Parallel Outputs
Q
0,Q7
Serial Outputs
Functional Description
The ’AC/’ACT299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S
0
and S1,as
shown in the Truth Table. All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q7are
also brought out on other pins for expansion in serial shifting
of longer words.
ALOW signal on MR overrides the Select and CP inputs and
resets the flip-flops. All other state changes are initiated by
the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times, relative to the rising edge of CP, are
observed.
AHIGH signal on either OE
1
or OE2disables the TRI-STATE
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can
still occur. The TRI-STATEbuffers are also disabled by HIGH
signals on both S
0
and S1in preparation for a parallel load
operation.
Truth Table
Inputs Response
MR
S1S0CP
L X X X Asynchronous Reset;
Q
0–Q7
=
LOW
HHH
N
Parallel Load; I/O
n
→
Q
n
HLH
N
Shift Right; DS
0
→
Q
0
,
Q
0
→
Q
1
, etc.
HHL
N
Shift Left, DS
7
→
Q
7
,
Q
7
→
Q
6
, etc.
H L L X Hold
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
N
=
LOW-to-HIGH Transition
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Logic Diagram
DS100252-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC+0.5V
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+0.5V
DC Output Source or Sink Current
(I
O
)
±
50 mA
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
±
50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
(Unless Otherwise Specified)
’AC 2.0V to 6.0V
’ACT 4.5V to 5.0V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA)
54AC/ACT −55˚C to +125˚C
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
V
IN
from 30%to 70%of V
CC
V
CC
@
3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Obviously the databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. National does
not recommend operation of FACT
®
circuits outside databook specifications.
DC Electrical Characteristics
For ’AC Family Devices
54AC
Symbol Parameter V
CC
T
A
=
Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
V
IH
Minimum High Level 3.0 2.1 V
OUT
=
0.1V
Input Voltage 4.5 3.15 V or V
CC
− 0.1V
5.5 3.85
V
IL
Maximum Low Level 3.0 0.9 V
OUT
=
0.1V
Input Voltage 4.5 1.35 V or V
CC
− 0.1V
5.5 1.65
V
OH
Minimum High Level 3.0 2.9 I
OUT
=
−50 µA
Output Voltage 4.5 4.4 V
5.5 5.4
(Note 2)
V
IN
=
V
IL
or V
IH
3.0 2.4 V I
OH
=
−12 mA
4.5 3.7 I
OH
=
−24 mA
5.5 4.7 I
OH
=
−24 mA
V
OL
Maximum Low Level 3.0 0.1 I
OUT
=
50 µA
Output Voltage 4.5 0.1 V
5.5 0.1
(Note 2)
V
IN
=
V
IL
or V
IH
3.0 0.50 I
OH
=
12 mA
4.5 0.50 V I
OH
=
24 mA
5.5 0.50 I
OH
=
24 mA
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
Note 2: All outputs loaded; threshold on input associated with output under test.
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DC Electrical Characteristics
For ’AC Family Devices
54AC
Symbol Parameter V
CC
T
A
=
Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
(Note 4)
I
OLD
Minimum Dynamic 5.5 50 mA V
OLD
=
1.65V Max
I
OHD
Output Current 5.5 −50 mA V
OHD
=
3.85V Min
I
CC
Maximum Quiescent 5.5 80.0 µA V
IN
=
V
CC
Supply Current or GND
I
OZT
Maximum I/O VI(OE)=VIL,V
IH
Leakage Current 5.5
±
5.5 µA V
I
=
V
CC
, GND
V
O
=
V
CC
, GND
Note 3: All outputs loaded; threshold on input associated with output under test.
Note 4: Maximum test duration 20 ms, one output loaded at a time.
Note 5: I
IN
and I
CC
@
3.0V are guaranteed to be less than or equal to the respective limit@5.5V VCC.
I
CC
for 54AC@25˚C is identical to 74AC@25˚C.
DC Electrical Characteristics
For ’ACT Family Devices
54ACT
Symbol Parameter V
CC
T
A
=
Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
V
IH
Minimum High Level 4.5 2.0 V V
OUT
=
0.1V
Input Voltage 5.5 2.0 or V
CC
− 0.1V
V
IL
Maximum Low Level 3.0 0.8 V
OUT
=
0.1V
Input Voltage 4.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High Level 4.5 4.4 V I
OUT
=
−50 µA
5.5 5.4
(Note 7)
V
IN
=
V
IL
or V
IH
4.5 3.70 V I
OH
=
−24 mA
5.5 4.70 I
OH
=
−24 mA
V
OL
Maximum Low Level 4.5 0.1 V I
OUT
=
50 µA
Output Voltage 5.5 0.1
(Note 7)
V
IN
=
V
IL
or V
IH
4.5 0.50 V I
OL
=
24 mA
5.5 0.50 I
OL
=
24 mA
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
I
CCT
Maximum ICC/Input 5.5 1.6 mA V
I
=
V
CC
− 2.1V
(Note 8)
I
OLD
Minimum Dynamic 5.5 50 mA V
OLD
=
1.65V Max
I
OHD
Output Current 5.5 −50 mA V
OHD
=
3.85V Min
I
CC
Maximum Quiescent 5.5 80.0 µA V
IN
=
V
CC
Supply Current or GND
I
OZT
Maximum I/O VI(OE)=VIL,V
IH
Leakage Current 5.5
±
5.0 µA V
I
=
V
CC
, GND
V
O
=
V
CC
, GND
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DC Electrical Characteristics (Continued)
Note 6: ICClimit for 54ACT@25˚C is identical to 74ACT@25˚C.
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
=
5.0V
C
PD
Power Dissipation 170 pF V
CC
=
5.5V
Capacitance
AC Electrical Characteristics
54AC
V
CC
T
A
=
−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 9) C
L
=
50 pF
Min Max
f
max
Maximum Input 3.3 70 MHz
Frequency 5.0 80
t
PLH
Propagation Delay 3.3 1.0 25.5
CP to Q
0
or Q
7
5.0 1.0 17.5 ns
(Shift Left or Right)
t
PHL
Propagation Delay 3.3 1.0 26.5
CP to Q
0
or Q
7
5.0 1.0 18.0 ns
(Shift Left or Right)
t
PLH
Propagation Delay 3.3 1.0 24.5 ns
CP to I/O
n
5.0 1.0 17.0
t
PHL
Propagation Delay 3.3 1.0 26.5 ns
CP to I/O
n
5.0 1.0 18.5
t
PHL
Propagation Delay 3.3 1.0 27.0 ns
MR to Q
0
or Q
7
5.0 1.0 18.5
t
PHL
Propagation Delay 3.3 1.0 26.5 ns
MR to I/O
n
5.0 1.0 18.0
t
PZH
Output Enable Time 3.3 1.0 22.0 ns
OE to I/O
n
5.0 1.0 15.0
t
PZL
Output Enable Time 3.3 1.0 23.5 ns
OE to I/O
n
5.0 1.0 16.0
t
PHZ
Output Disable Time 3.3 1.0 22.5 ns
OE to I/O
n
5.0 1.0 17.0
t
PLZ
Output Disable Time 3.3 1.0 21.5 ns
OE to I/O
n
5.0 1.0 16.0
Note 9: Voltage Range 3.3 is 3.3V±0.3V.
Voltage Range 5.0 is 5.0V
±
0.5V.
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AC Operating Requirements
54AC
V
CC
T
A
=
−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 10) C
L
=
50 pF
Guaranteed
Minimum
t
s
Setup Time, HIGH or LOW 3.3 9.5 ns
S
0
or S1to CP 5.0 7.0
t
h
Hold Time, HIGH or LOW 3.3 2.0 ns
S
0
or S1to CP 5.0 2.5
t
s
Setup Time, HIGH or LOW 3.3 6.0 ns
I/O
n
to CP 5.0 4.0
t
h
Hold Time, HIGH or LOW 3.3 1.5 ns
I/O
n
to CP 5.0 2.0
t
s
Setup Time, HIGH or LOW 3.3 7.5 ns
DS
0
or DS7to CP 5.0 5.0
t
h
Hold Time, HIGH or LOW 3.3 1.5 ns
DS
0
or DS7to CP 5.0 1.5
t
w
CP Pulse Width, LOW 3.3 5.5 ns
5.0 5.0
t
w
MR Pulse Width, LOW 3.3 5.5 ns
5.0 5.0
t
rec
Recovery Time 3.3 2.5 ns
MR to CP
5.0 2.5
Note 10: Voltage Range 3.3 is 3.3V±0.3V
Voltage Range 5.0 is 5.0V
±
0.5V
AC Electrical Characteristics
54ACT
V
CC
T
A
=
−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 11) C
L
=
50 pF
Min Max
f
max
Maximum Input 5.0 70 MHz
Frequency
t
PLH
Propagation Delay
CP to Q
0
or Q
7
5.0 1.0 15.5 ns
(Shift Left or Right)
t
PHL
Propagation Delay
CP to Q
0
or Q
7
5.0 1.0 16.0 ns
(Shift Left or Right)
t
PLH
Propagation Delay 5.0 1.0 15.0 ns
CP to I/O
n
t
PHL
Propagation Delay 5.0 1.0 18.0 ns
CP to I/O
n
t
PHL
Propagation Delay 5.0 1.0 18.0 ns
MR to Q
0
or Q
7
t
PHL
Propagation Delay 5.0 1.0 17.5 ns
MR to I/O
n
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Page 8
AC Electrical Characteristics (Continued)
54ACT
V
CC
T
A
=
−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 11) C
L
=
50 pF
Min Max
t
PZH
Output Enable Time 5.0 1.0 14.0 ns
OE to I/O
n
t
PZL
Output Enable Time 5.0 1.0 14.5 ns
OE to I/O
n
t
PHZ
Output Disable Time 5.0 1.0 14.5 ns
OE to I/O
n
t
PLZ
Output Disable Time 5.0 1.0 14.0 ns
OE to I/O
n
Note 11: Voltage Range 5.0 is 5.0V±0.5V
AC Operating Requirements
54ACT
V
CC
T
A
=
−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 12) C
L
=
50 pF
Guaranteed
Minimum
t
s
Setup Time, HIGH or LOW 5.0 6.5 ns
S
0
or S1to CP
t
h
Hold Time, HIGH or LOW 5.0 1.5 ns
S
0
or S1to CP
t
s
Setup Time, HIGH or LOW 5.0 4.5 ns
I/O
n
to CP
t
h
Hold Time, HIGH or LOW 5.0 1.5 ns
I/O
n
to CP
t
s
Setup Time, HIGH or LOW 5.0 5.5 ns
DS
0
or DS7to CP
t
h
Hold Time, HIGH or LOW 5.0 1.5 ns
DS
0
or DS7to CP
t
w
CP Pulse Width 5.0 5.0 ns
HIGH or LOW
t
w
MR Pulse Width, LOW 5.0 5.0 ns
t
rec
Recovery Time 5.0 1.5 ns
MR to CP
Note 12: Voltage Range 5.0 is 5.0V±0.5V.
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Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (LCC)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J20A
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Page 10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
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Email: support@nsc.com
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Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
20 Lead Ceramic FLATPAK
NS Package Number W20A
54ACC299
•
54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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