Datasheet 5962R9160301VFA, 5962R9160301VEA, 5962R9160301V2A, 5962R9160301MFA, 5962R9160301MEA Datasheet (NSC)

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54AC169•54ACT169 4-Stage Synchronous Bidirectional Counter

General Description

The ’AC/’ACT169 is fully synchronous 4-stage up/down counter. The ’AC/’ACT169 is a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock.

Features

n ICCreduced by 50

n Synchronous counting and loading n Built-In lookahead carry capability n Presettable for programmable operation n Outputs source/sink 24 mA n ’ACT has TTL-compatible inputs n Standard Microcircuit Drawing (SMD)

5962-91603

Logic Symbols

Names

Description

CEP

Count Enable Parallel Input

CET

Count Enable Trickle Input CP Clock Pulse Input P

0–P3

Parallel Data Inputs PE

Parallel Enable Input U/D

Up-Down Count Control Input Q

0–Q3

Flip-Flop Outputs TC

Terminal Count Output

FACT™is a trademark of Fairchild Semiconductor Corporation.

DS100276-1

IEEE/IEC

DS100276-2

July 1998

54AC169

•

54ACT169 4-Stage Synchronous Bidirectional Counter

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Connection Diagrams

Logic Diagram

Functional Description

The ’AC/’ACT169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table.When PE is LOW, the

data on the P0–P3inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. If an illegal state occurs, the ’AC169 will return to the legitimate sequence within two counts. Since

Pin Assignment

for DIP and Flatpak

DS100276-3

Pin Assignment

for LCC

DS100276-4

DS100276-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Functional Description (Continued)

the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below).

1. Count Enable=CEP

•

CET•PE

2. Up: TC=Q

•

Q2Q

•

(Up)•CET

3. Down: TC=Q

•

(Down)•CET

Mode Select Table

PE CEP CET U/D Action on Rising

Clock Edge

L X X X Load (P

to Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold)

H=HIGH Voltage Level L=LOW Voltage Level X=Immaterial

State Diagrams

DS100276-6

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V

) −0.5V to +7.0V

DC Input Diode Current (I

)

−0.5V −20 mA

+ 0.5V +20 mA

DC Input Voltage (V

) −0.5V to VCC+ 0.5V

DC Output Diode Current (I

)

−0.5V −20 mA

+ 0.5V +20 mA

DC Output Voltage (V

) −0.5V to VCC+ 0.5V

DC Output Source

or Sink Current (I

)

50 mA

DC V

or Ground Current

per Output Pin (I

or I

GND

)

50 mA

Storage Temperature (T

STG

) −65˚C to +150˚C

Junction Temperature (T

)

CDIP 175˚C

Recommended Operating Conditions

Supply Voltage (VCC)

’AC 2.0V to 6.0V ’ACT 4.5V to 5.5V

Input Voltage (V

) 0VtoV

Output Voltage (VO) 0VtoV

Operating Temperature (TA)

54AC/ACT −55˚C to +125˚C

Minimum Input Edge Rate (∆V/∆t)

’AC Devices V

from 30%to 70%of V

3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

’ACT Devices V

from 0.8V to 2.0V

4.5V, 5.5V 125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT

™

circuits outside databook specifications.

DC Characteristics for ’AC Family Devices

54AC

Symbol Parameter V

Units Conditions

(V) −55˚C to +125˚C

Guaranteed

Limits

Minimum High Level 3.0 2.1 V

OUT

0.1V

Input Voltage 4.5 3.15 V or V

− 0.1V

5.5 3.85

Maximum Low Level 3.0 0.9 V

OUT

0.1V

Input Voltage 4.5 1.35 V or V

− 0.1V

5.5 1.65

Minimum High Level 3.0 2.9 I

OUT

−50 µA

Output Voltage 4.5 4.4 V

5.5 5.4 (Note 2)

or V

3.0 2.4 IOH= −12 mA

4.5 3.7 V I

= −24 mA

5.5 4.7 I

= −24 mA

Maximum Low Level 3.0 0.1 I

OUT

50 µA

Output Voltage 4.5 0.1 V

5.5 0.1 (Note 2)

or V

3.0 0.50 IOL=12mA

4.5 0.50 V I

=24mA

5.5 0.50 I

=24mA

Maximum Input 5.5

1.0 µA V

, GND

Leakage Current

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DC Characteristics for ’AC Family Devices (Continued)

54AC

Symbol Parameter V

Units Conditions

(V) −55˚C to +125˚C

Guaranteed

Limits

OLD

Minimum Dynamic Output Current (Note 3)

5.5 50 mA V

OLD

1.65V Max

OHD

5.5 −50 mA V

OHD

3.85V Min

Maximum Quiescent 5.5 80.0 µA V

Supply Current or GND

Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: I

and I

3.0V are guaranteed to be less than or equal to the respective limit@5.5V VCC.

for 54AC@25˚C is identical to 74AC@25˚C.

DC Characteristics for ’ACT Family Devices

54ACT

Symbol Parameter V

Units Conditions

(V) −55˚C to +125˚C

Guaranteed

Limits

Minimum High Level 4.5 2.0 V V

OUT

0.1V

Input Voltage 5.5 2.0 or V

− 0.1V

Maximum Low Level 4.5 0.8 V V

OUT

0.1V

Input Voltage 5.5 0.8 or V

− 0.1V

Minimum High Level 4.5 4.4 V I

OUT

−50 µA

Output Voltage 5.5 5.4

(Note 5) V

or V

4.5 3.70 V IOH= −24 mA

5.5 4.70 I

= −24 mA

Maximum Low Level 4.5 0.1 V I

OUT

50 µA

Output Voltage 5.5 0.1

(Note 5) V

or V

4.5 0.50 V IOL=24mA

5.5 0.50 I

=24mA

Maximum Input 5.5

1.0 µA V

, GND

Leakage Current

CCT

Maximum 5.5 1.6 mA V

− 2.1V

/Input

OLD

Minimum Dynamic Output Current (Note 6)

5.5 50 mA V

OLD

1.65V Max

OHD

5.5 −50 mA V

OHD

3.85V Min

Maximum Quiescent 5.5 80.0 µA V

Supply Current or GND

Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: I

for 54ACT@25˚C is identical to 74ACT@25˚C.

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AC Electrical Characteristics

54AC

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 8) C

50 pF

Min Max

max

Maximum Clock 3.3 55 MHz Frequency 5.0 75

PLH

Propagation Delay 3.3 1.0 15.0 CP to Q

5.0 1.5 12.0 ns

(PE HIGH or LOW)

PHL

Propagation Delay 3.3 1.0 16.5 CP to Q

5.0 1.5 13.0 ns

(PE HIGH or LOW)

PLH

Propagation Delay 3.3 3.0 22.0 ns CP to TC

5.0 3.0 16.0

PHL

Propagation Delay 3.3 3.0 22.0 ns CP to TC

5.0 3.0 16.0

PLH

Propagation Delay 3.3 1.0 18.5 ns CET to TC

5.0 1.5 13.0

PHL

Propagation Delay 3.3 1.0 16.0 ns CET to TC

5.0 1.5 11.0

PLH

Propagation Delay 3.3 1.0 18.5 ns U/D to TC

5.0 1.5 13.0

PHL

Propagation Delay 3.3 1.0 16.5 ns U/D to TC

5.0 1.5 12.0

Note 8: Voltage Range 3.3 is 3.3V±0.3V Voltage Range 5.0 is 5.0V

0.5V

AC Operating Requirements

54AC

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 9) C

50 pF

Guaranteed

Minimum

Setup Time, 3.3 7.0 HIGH or LOW 5.0 4.5 ns P

to CP

Hold Time, HIGH or LOW 3.3 2.0 ns P

to CP 5.0 2.5

Setup Time, 3.3 13.5 HIGH or LOW 5.0 9.0 ns CEP to CP

Hold Time, HIGH or LOW 3.3 0.5 ns CEP to CP

5.0 2.5

Setup Time, 3.3 13.5 HIGH or LOW 5.0 9.0 ns CET to CP

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AC Operating Requirements (Continued)

54AC

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 9) C

50 pF

Guaranteed

Minimum

Hold Time, HIGH or LOW 3.3 0.5 ns CET to CP

5.0 2.5

Setup Time, 3.3 8.5 HIGH or LOW 5.0 6.5 ns PE to CP

Hold Time, HIGH or LOW 3.3 0.5 ns PE to CP

5.0 2.0

Setup Time, 3.3 13.0 HIGH or LOW 5.0 9.0 ns U/D to CP

Hold Time, HIGH or LOW 3.3 0.5 ns U/D to CP

5.0 2.0

CP Pulse Width, 3.3 5.0 ns HIGH or LOW 5.0 5.0

Note 9: Voltage Range 3.3 is 3.3V±0.3V Voltage Range 5.0 is 5.0V

0.5V

AC Electrical Characteristics

54ACT

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 10) C

50 pF

Min Max

max

Maximum Clock 5.0 75 MHz Frequency

PLH

Propagation Delay CP to Q

5.0 1.5 12.5 ns

(PE HIGH or LOW)

PHL

Propagation Delay CP to Q

5.0 1.5 12.5 ns

(PE HIGH or LOW)

PLH

Propagation Delay 5.0 1.5 16.5 ns CP to TC

PHL

Propagation Delay 5.0 1.5 16.5 ns CP to TC

PLH

Propagation Delay 5.0 1.5 13.5 ns CET to TC

PHL

Propagation Delay 5.0 1.5 13.5 ns CET to TC

PLH

Propagation Delay 5.0 1.5 14.5 ns U/D to TC

PHL

Propagation Delay 5.0 1.5 14.5 ns U/D to TC

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AC Electrical Characteristics (Continued)

Note 10: Voltage Range 5.0 is 5.0V±0.5V

AC Operating Requirements

54ACT

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 11) C

50 pF

Guaranteed

Minimum

Setup Time, HIGH or LOW 5.0 4.5 ns P

to CP

Hold Time, HIGH or LOW 5.0 2.5 ns P

to CP

Setup Time, HIGH or LOW 5.0 9.0 ns CEP to CP

Hold Time, HIGH or LOW 5.0 2.5 ns CEP to CP

Setup Time, HIGH or LOW 5.0 9.0 ns CET to CP

Hold Time, HIGH or LOW 5.0 2.5 ns CET to CP

Setup Time, HIGH or LOW 5.0 6.5 ns PE to CP

Hold Time, HIGH or LOW 5.0 2.0 ns PE to CP

Setup Time, HIGH or LOW 5.0 9.0 ns U/D to CP

Hold Time, HIGH or LOW 5.0 2.0 ns U/D to CP

CP Pulse Width, 5.0 5.0 ns HIGH or LOW

Note 11: Voltage Range 5.0 is 5.0V±0.5V

Capacitance

Symbol Parameter Typ Units Conditions

Input Capacitance 4.5 pF V

Open

Power Dissipation 60.0 pF V

5.0V

Capacitance

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Physical Dimensions inches (millimeters) unless otherwise noted

20-Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

16-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J16A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

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1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com

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Tel: 81-3-5620-6175 Fax: 81-3-5620-6179

16-Lead Ceramic Flatpak (F)

NS Package Number W16A

54AC169

•

54ACT169 4-Stage Synchronous Bidirectional Counter

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.