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54ABT652
Octal Transceivers and Registers with TRI-STATE
®
Outputs
General Description
The ’ABT652 consists of bus transceiver circuits with D-type
flip-flops, andcontrolcircuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the
registers as the appropriate clock pin goes to HIGH logic
level. Output Enable pins (OEAB, OEBA) are provided to
control the transceiver function.
Features
n Independent registers for A and B buses
n Multiplexed real-time and stored data
n A and B output sink capability of 48 mA, source
capability of 24 mA
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Nondestructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9324201
Ordering Code:
Commercial Package Package Description
Number
54ABT652J-QML J24A 24-Lead Ceramic Dual-in-line
54ABT652W-QML W24C 24-Lead Cerpack
54ABT652E-QML E28A 28-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagram
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
Pin Assignment for
DIP and Flatpack
DS100220-1
August 1998
54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100220 www.national.com
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Connection Diagram (Continued)
Pin Assignment for LCC
DS100220-48
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Pin Descriptions
Pin Names Description
A
0–A7
Data Register A Inputs/TRI-STATE Outputs
B
0–B7
Data Register B Inputs/TRI-STATE Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Select Inputs
OEAB, OEBA
Output Enable Inputs
Logic Diagram
Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in
Figure 1
demonstrate the four fundamental
bus-management functions that can be performed with the
’ABT652C.
Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropri-
ate Clock Inputs (CPAB, CPBA) regardless of the Select or
Output Enable Inputs. When SAB and SBA are in the real
time transfer mode, it is also possible to store data without
using the internal D flip-flops by simultaneously enabling
OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two
sets of bus lines are in a HIGH impedance state, each set of
bus lines will remain at its last state.
DS100220-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Functional Description (Continued)
Note A: Real-Time
Transfer Bus B to Bus A
DS100220-4
OEAB OEBA CPAB CPBA SAB SBA
LLXXXL
Note C: Storage
DS100220-6
OEAB OEBA CPAB CPBA SAB SBA
XHNXXX
LXXNXX
LHNNXX
Note B: Real-Time
Transfer Bus A to Bus B
DS100220-5
OEAB OEBA CPAB CPBA SAB SBA
HHXXLX
Note D: Transfer Storage
Data to A or B
DS100220-7
OEAB OEBA CPAB CPBA SAB SBA
H L HorL HorL H H
FIGURE 1.
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Functional Description (Continued)
Inputs Inputs/Outputs (Note 1) Operating Mode
OEAB OEBA
CPAB CPBA SAB SBA A0thru A
7
B0thru B
7
L H H or L H or L X X Input Input Isolation
L H N N X X Store A and B Data
X H N H or L X X Input Not Specified Store A, Hold B
H H N N X X Input Output Store A in Both Registers
L X H or L N X X Not Specified Input Hold A, Store B
L L N N X X Output Input Store B in Both Registers
L L X X X L Output Input Real-Time B Data to A Bus
L L X H or L X H Store B Data to A Bus
H H X X L X Input Output Real-Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
Stored B Data to A Bus
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
N=LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at
the bus pins will be stored on every LOW to HIGH transition on the clock inputs.
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Absolute Maximum Ratings (Note 2)
Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias
Ceramic −55˚C to +175˚C
V
CC
Pin Potential to
Ground Pin −0.5V to +7.0V
Input Voltage (Note 3) −0.5V to +7.0V
Input Current (Note 3) −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disable or
or Power-Off State −0.5V to +5.5V
in the HIGH State −0.5V to V
CC
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
DC Latchup Source Current −500 mA
Over Voltage Latchup (I/O) 10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military −55˚C to +125˚C
Supply Voltage
Military +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
Clock Input 100 mV/ns
Note 2: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol Parameter ABT652 Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min I
IN
=
−18 mA (Non I/O Pins)
V
OH
Output HIGH 54ABT 2.5 V Min I
OH
=
−3 mA, (A
n,Bn
)
Voltage 54ABT 2.0 I
OH
=
−24 mA, (A
n,Bn
)
V
OL
Output LOW 54ABT 0.55 V Min I
OL
=
48 mA, (A
n,Bn
)
Voltage
I
IH
Input HIGH Current 2 µA Max V
IN
=
2.7V (Non-I/O Pins) (Note 4)
V
IN
=
V
CC
(Non-I/O Pins)
I
BVI
Input HIGH Current 7 µA Max V
IN
=
7.0V (Non-I/O Pins)
Breakdown Test
I
BVIT
Input HIGH Current 100 µA Max V
IN
=
5.5V (A
n,Bn
)
Breakdown Test (I/O)
I
IL
Input LOW Current −2 µA Max V
IN
=
0.5V (Non-I/O Pins) (Note 4)
V
IN
=
0.0V (Non-I/O Pins)
I
IH+IOZH
Output Leakage Current 50 µA 0V–5.5V V
OUT
=
2.7V (A
n,Bn
);
OEBA=2.0V and OEAB=GND=2.0V
IIL+I
OZL
Output Leakage Current −50 µA 0V–5.5V V
OUT
=
0.5V (A
n,Bn
);
OEBA=2.0V and OEAB=GND=2.0V
I
OS
Output Short-Circuit Current −50 −180 mA Max V
OUT
=
0V (A
n,Bn
)
I
CEX
Output HIGH Leakage Current 50 µA Max V
OUT
=
V
CC(An,Bn
)
I
CCH
Power Supply Current 250 µA Max All Outputs HIGH
I
CCL
Power Supply Current 30 mA Max All Outputs LOW
I
CCZ
Power Supply Current 250 µA Max Outputs TRI-STATE;
All others at V
CC
or GND
I
CCT
Additional ICC/Input 2.5 mA Max V
I
=
V
CC
− 2.1V
All others at V
CC
or GND
Note 4: Guaranteed but not tested.
Note 5: For 8 outputs toggling, I
CCD
<
1.4 mA/MHz.
Note 6: Guaranteed, but not tested.
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DC Electrical Characteristics
Symbol Parameter Max Units V
CC
Conditions
C
L
=
50 pF, R
L
=
500Ω
V
OLP
Quiet Output Maximum Dynamic V
OL
1.2 V 5.0 T
A
=
25˚C (Note 7)
V
OLV
Quiet Output Minimum Dynamic V
OL
-1.8 V 5.0 T
A
=
25˚C (Note 7)
Note 7: Max number of outputs defined as (n).n−1data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
AC Electrical Characteristics
54ABT
T
A
=
−55˚C to +125˚C Fig.
Symbol Parameter V
CC
=
4.5V–5.5V Units No.
C
L
=
50 pF
Min Max
f
max
Max Clock Frequency 125 MHz
t
PLH
Propagation Delay 1.4 7.8 ns
Figure
5
t
PHL
Clock to Bus 1.2 8.4
t
PLH
Propagation Delay 1.5 6.7 ns
Figure
5
t
PHL
Bus to Bus 1.5 6.7
t
PLH
Propagation Delay 1.2 6.9 ns
Figure
5
t
PHL
SBA or SAB to Anto B
n
1.2 7.7
t
PZH
Enable Time 1.3 5.6
ns
Figure
7
t
PZL
OEBA or OEAB to Anor B
n
2.0 7.8
t
PHZ
Disable Time 1.5 8.2
ns
Figure
7
t
PLZ
OEBA or OEAB to Anor B
n
1.5 7.3
AC Operating Requirements
54ABT
T
A
=
−55˚C to +125˚C Fig.
Symbol Parameter V
CC
=
4.5V–5.5V Units No.
C
L
=
50 pF
Min Max
t
S
(H) Setup Time, HIGH
3.5 ns
Figure
8
tS(L) or LOW Bus to Clock
t
H
(H) Hold Time, HIGH
1.5 ns
Figure
8
tH(L) or LOW Bus to Clock
t
W
(H) Pulse Width,
4.0 ns
Figure
6
tW(L) HIGH or LOW
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Capacitance
Symbol Parameter Max Units Conditions
(T
A
=
25˚C)
C
IN
Input Capacitance 14.0 pF V
CC
=
0V (non I/O pins)
C
I/O
(Note 8) I/O Capacitance 19.5 pF V
CC
=
5.0V (A
n,Bn
)
Note 8: C
I/O
is measured at frequency, f=1 MHz, per MIL-STD-883D, Method 3012.
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Capacitance (Continued)
t
PLH
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
Clock to Bus
DS100220-16
t
PHL
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
Clock to Bus
DS100220-17
t
PLH
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
Bus to Bus
DS100220-18
t
PHL
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
Bus to Bus
DS100220-19
t
PLH
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
SBA or SAB to A
n
or B
n
DS100220-20
t
PHL
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
SBA or SAB to A
n
or B
n
DS100220-21
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Capacitance (Continued)
t
PLH
vs Load Capacitance
1 Output Switching, T
A
=
25˚C
Clock to Bus
DS100220-22
t
PHL
vs Load Capacitance
1 Output Switching, T
A
=
25˚C
Clock to Bus
DS100220-23
t
PLH
vs Load Capacitance
1 Output Switching, T
A
=
25˚C
Bus to Bus
DS100220-24
t
PHL
vs Load Capacitance
1 Output Switching, T
A
=
25˚C
Bus to Bus
DS100220-25
t
PLH
vs Load Capacitance
1 Output Switching, T
A
=
25˚C
SBA or SAB to A
n
or B
n
DS100220-26
t
PHL
vs Load Capacitance
1 Output Switching, T
A
=
25˚C
SBA or SAB to A
n
or B
n
DS100220-27
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Capacitance (Continued)
t
PLH
vs Load Capacitance
8 Outputs Switching, T
A
=
25˚C
Clock to Bus
DS100220-28
t
PHL
vs Load Capacitance
8 Outputs Switching, T
A
=
25˚C
Clock to Bus
DS100220-29
t
PLH
vs Load Capacitance
8 Outputs Switching, T
A
=
25˚C
Bus to Bus
DS100220-30
t
PHL
vs Load Capacitance
8 Outputs Switching, T
A
=
25˚C
Bus to Bus
DS100220-31
t
PLH
vs Load Capacitance
8 Outputs Switching, T
A
=
25˚C
SBA or SAB to A
n
or B
n
DS100220-32
t
PHL
vs Load Capacitance
8 Outputs Switching, T
A
=
25˚C
SBA or SAB to A
n
or B
n
DS100220-33
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Capacitance (Continued)
t
PZL
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
DS100220-34
t
PLZ
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
DS100220-35
t
PZH
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
DS100220-36
t
PHZ
vs Temperature (TA)
C
L
=
50 pF, 1 Output Switching
DS100220-37
t
PZH
vs Temperature (TA)
C
L
=
50 pF, 8 Outputs Switching
DS100220-38
t
PHZ
vs Temperature (TA)
C
L
=
50 pF, 8 Outputs Switching
DS100220-39
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Capacitance (Continued)
t
PZL
vs Temperature (TA)
C
L
=
50 pF, 8 Outputs Switching
DS100220-40
t
PLZ
vs Temperature (TA)
C
L
=
50 pF, 8 Outputs Switching
DS100220-41
t
PZL
vs Load Capacitance
8 Outputs Switching
T
A
=
25˚C
DS100220-42
t
PZH
vs Load Capacitance
8 Outputs Switching
T
A
=
25˚C
DS100220-43
t
PLH
and t
PHL
vs Number Output Switching
V
CC
=
5V, T
A
=
25˚C, C
L
=
50 pF
Clock to Bus
DS100220-44
t
PLH
and t
PHL
vs Number Output Switching
V
CC
=
5V, T
A
=
25˚C, C
L
=
50 pF
Bus to Bus
DS100220-45
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Capacitance (Continued)
t
PLH
and t
PHL
vs Number Output Switching
V
CC
=
5V, T
A
=
25˚C, C
L
=
50 pF
SBA or SAB to A
n
or B
n
DS100220-46
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AC Loading
DS100220-8
*
Includes jig and probe capacitance
FIGURE 2. Standard AC Test Load
DS100220-10
FIGURE 3. Test Input Signal Levels
Input Pulse Requirements
Amplitude Rep. Rate t
w
t
r
t
f
3.0V 1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 4. Test Input Signal Requirements
DS100220-12
FIGURE 5. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
DS100220-9
FIGURE 6. Propagation Delay,
Pulse Width Waveforms
DS100220-11
FIGURE 7. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100220-13
FIGURE 8. Setup Time, Hold Time
and Recovery Time Waveforms
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Ceramic Dual-in-line
NS Package Number J24A
24-Lead Cerpack
NS Package Number W24C
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
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Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
28-Lead Ceramic Leadless Chip Carrier, Type C
NS Package Number E28A
54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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