Datasheet AS4C4M4E1Q-60TC, AS4C4M4E1Q-60JC, AS4C4M4E1Q-50TC, AS4C4M4E1Q-50JC, 4C4M4EOQ-60TC Datasheet (Alliance Semiconductor Corporation)
...Page 1
March 2001
Copyright © Alliance Semiconductor. All rights reserved.
®
AS4C4M4EOQ
AS4C4M4E1Q
4M ✕ 4 CMOS QuadCAS DRAM (EDO) family
3/22/01; v.1.0
Alliance Semiconductor
P. 1 of 16
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS
access time
- 25/30 ns column address access time
- 12/15 ns CAS
access time
• Low power consumption
- Active: 495 mW max
- Standby: 5.5 mW max, CMOS I/O
• Extended data out
•Refresh
- 4096 refresh cycles, 64 ms refresh interval for
4C4M4EOQ
- 2048 refresh cycles, 32 ms refresh interval for
AS4C4M4E1Q
-RAS
-only and hidden refresh or CAS-before-RAS refresh
or self-refresh
• TTL-compatible
•4 separate CAS
pins allow for separate I/O operation
• JEDEC standard package
- 300 mil, 28-pin SOJ
- 300 mil, 28-pin TSOP
• 5V power supply
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 mV
Pin arrangement
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
V
CC
GND
GND
I/O3
I/O2
CAS
3
OE
V
CC
I/O0
I/O1
WE
RAS
1
2
3
4
5
28
27
26
25
24
*NC/A11 A9623
9
10
11
12
13
20
19
18
17
16
14 15
SOJ
AS4C4M4E0
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
V
CC
GND
GND
I/O3
I/O2
CAS
3
OE
V
CC
I/O0
I/O1
WE
RAS
1
2
3
4
5
28
27
26
25
24
*NC/A11 A9
623
9
10
11
12
13
20
19
18
17
16
14 15
TSOP
AS4C4M4E0
* NC on 2K refresh version; A11 on 4K refresh version
CAS0
CAS
1
7
8
CAS2
22
21
NC
CAS0
CAS
1
7
8
NC
22
21
CAS
2
Pin designation
Pin(s) Description
A0 to A11 Address inputs
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
I/O0 to I/O3 Input/output
OE
Output enable
V
CC
Power
GND Ground
NC No Connection
Selection guide
Symbol 4C4M4EOQ/E1Q-50 4C4M4EOQ/E1-60 Unit
Maximum RAS
access time t
RAC
50 60 ns
Maximum column address access time t
CAA
25 30 ns
Maximum CAS
access time t
CAC
12 15 ns
Maximum output enable (OE
) access time t
OEA
13 15 ns
Minimum read or write cycle time t
RC
85 100 ns
Minimum hyper page mode cycle time t
PC
20 24 ns
Maximum operating current I
CC1
110 100 mA
Maximum CMOS standby current I
CC5
1.0 1.0 mA
Page 2
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P. 2 of 16
Functional description
The 4C4M4EOQ, and AS4C4M4E1Q are high performance 16-megabit CMOS Quad CAS Dynamic Random Access Memories (DRAM)
organized as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques
resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family
is optimized for use as main memory in PC, workstation, router and switch applications.
These products feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS
and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
column addresses prior to CAS
assertion.
Extended data out (EDO) read mode enables 50 MHz operation using 50 ns devices. Four individual CAS pins allow for separate I/O
operation which enables the device to operate in parity mode. In contrast to 'fast page mode' devices, data remains active on outputs after
CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus
contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS
and CAS
going high.
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:
•RAS
-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS
is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
•CAS
-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE
and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
•RAS
-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS
is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
•CAS
-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE
and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The 4C4M4EOQ and AS4C4M4E1Q are available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The 4C4M4EOQ and
AS4C4M4E1Q operate with a single power supply of 5V ± 0.5V. All provide TTL compatible inputs and outputs.
Page 3
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P. 3 of 16
Logic block diagram for 4K refresh
Logic block diagram for 2K refresh
Recommended operating conditions
†
VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
Parameter Symbol Min Nominal Max Unit
Supply voltage
4C4M4EOQ
AS4C4M4E1Q
V
CC
4.5 5.0 5.5 V
GND 0.0 0.0 0.0 V
Input voltage
4C4M4EOQ
AS4C4M4E1Q
V
IH
2.4 – V
CC
V
V
IL
–0.5
†
–0.8V
Ambient operating temperature T
A
070°C
RAS clock
generator
Refresh
controller
4,194,304 × 4
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
Address buffers
A8
Row decoder
Column decoder
Data
I/O
buffers
OE
RAS
CAS
WE clock
generator
WE
I/O0 to I/O3
CAS clock
generator
A9
A10
A11
RAS clock
generator
Refresh
controller
4,194,304 × 4
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
Address buffers
A8
Row decoder
Column decoder
Substrate bias
generator
Data
I/O
buffers
OE
RAS
CAS
WE clock
generator
WE
I/O0 to I/O3
CAS clock
generator
A9
A10
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P. 4 of 16
Absolute maximum ratings
DC electrical characteristics (AS4C4M4E0/E1)
Parameter Symbol Min Max Unit
Input voltage V
in
-1.0 +7.0 V
Input voltage (DQs) V
DQ
-1.0 VCC + 0.5 V
Power supply voltage V
CC
-1.0 +7.0 V
Storage temperature (plastic) T
STG
-55 +150 °C
Soldering temperature × time T
SOLDER
–260 × 10
o
C × sec
Power dissipation P
D
–1W
Short circuit output current I
out
–50mA
Parameter Symbol Test conditions
-50 -60
Unit NotesMin Max Min Max
Input leakage current I
IL
0V ≤ Vin ≤ +5.5V,
Pins not under test = 0V
-5 +5 -5 +5 µA
Output leakage current I
OL
D
OUT
disabled, 0V ≤ V
out
≤ +5.5V -5 +5 -5 +5 µA
Operating power
supply current
I
CC1
RAS, UCAS, LCAS, Address cycling;
t
RC
=min
– 110 – 100 mA 1,2
TTL standby power
supply current
I
CC2
RAS = UCAS = LCAS ≥ V
IH
–2.0 – 2.0mA
Average power supply
current, RAS
refresh
mode or CBR
I
CC3
RAS cycling, UCAS = LCAS ≥ V
IH
,
t
RC
= min of RAS low after XCAS
low.
– 110 – 100 mA 1
EDO page mode
average power supply
current
I
CC4
RAS = VIL, UCAS or LCAS,
address cycling: t
HPC
= min
–90 – 80mA1, 2
CMOS standby power
supply current
I
CC5
RAS = UCAS = LCAS = VCC - 0.2V – 1.0 – 1.0 mA
Output voltage
V
OH
I
OUT
= -5.0 mA 2.4 – 2.4 – V
V
OL
I
OUT
= 4.2 mA – 0.4 – 0.4 V
CAS
before RAS refresh
current
I
CC6
RAS, UCAS or LCAS cycling, tRC =
min
– 110 – 100 mA
Self refresh current I
CC7
RAS = UCAS = LCAS ≤ 0.2V,
WE
= OE ≥ V
CC
- 0.2V,
all other inputs at 0.2V or
V
CC
- 0.2V
–0.6 – 0.6
mA
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P. 5 of 16
DC electrical characteristics (AS4LC4M4E0/E1)
Parameter Symbol Test conditions
-50 -60
Unit NotesMin Max Min Max
Input leakag
e c
urrent I
IL
0V ≤ Vin ≤ V
CC
(max)
Pins not under test = 0V
-5 +5 -5 +5
µ
A
Output leakage current I
OL
D
OUT
disabled, 0V ≤ V
out
≤ V
CC
(max)
-5 +5 -5 +5
µ
A
Operating power
supply current
I
CC1
RAS, UCAS, LCAS, Address cycling;
t
RC
=min
– 85 – 75 mA 4,5
TTL standby power
supply current
I
CC2
RAS = UCAS = LCAS ≥ V
IH
,
all other inputs at V
IH
or V
IL
–2.0–2.0mA
Average power supply
current, RAS
refresh
mode or CBR
I
CC3
RAS cycling, UCAS = LCAS ≥ V
IH
,
t
RC
= min of RAS low after XCAS low.
–80–70mA4
EDO page mode
average power supply
current
I
CC4
RAS = VIL, UCAS or LCAS,
address cycling: t
HPC
= min
– 85 – 75 mA 4, 5
CMOS standby power
supply current
I
CC5
RAS = UCAS = LCAS = VCC - 0.2V,
F = 0
–200–200µA
Output voltage
V
OH
I
OUT
= -2.0 mA 2.4 – 2.4 – V
V
OL
I
OUT
= 2 mA –0.4–0.4V
CAS
before RAS refresh
current
I
CC6
RAS, UCAS or LCAS cycling, tRC =
min
–80–70
mA
Self refresh current I
CC7
RAS = UCAS = LCAS ≤ 0.2V,
WE
= OE = VCC - 0.2V,
all other inputs at 0.2V or V
CC
-
0.2V
–0.3–0.3
mA
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P. 6 of 16
AC parameters common to all waveforms
Read cycle
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
RC
Random read or write cycle time 80 – 100 – ns
t
RP
RAS precharge time 30 – 40 – ns
t
RAS
RAS pulse width 50 10K 60 10K ns
t
CAS
CAS pulse width 8 10K 10 10K ns
t
RCD
RAS to CAS delay time 15 35 15 43 ns 6
t
RAD
RAS to column address delay time 12 25 12 30 ns 7
t
RSH
CAS to RAS hold time 10 – 10 – ns
t
CSH
RAS to CAS hold time 40 – 50 – ns
t
CRP
CAS to RAS precharge time 5 – 5 – ns
t
ASR
Row address setup time 0 – 0 – ns
t
RAH
Row address hold time 8 – 10 – ns
t
T
Transition time (rise and fall) 1 50 1 50 ns 4,5
t
REF
Refresh period – 32/64 – 32/64 ms 17/16
t
CP
CAS precharge time 8 – 10 – ns
t
RAL
Column address to RAS lead time 25 – 30 – ns
t
ASC
Column address setup time 0 – 0 – ns
t
CAH
Column address hold time 8 10 – ns
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
RAC
Access time from RAS –50–60ns6
t
CAC
Access time from CAS – 12 – 15 ns 6,13
t
AA
Access time from address – 25 – 30 ns 7,13
t
RCS
Read command setup time 0 – 0 – ns
t
RCH
Read command hold time to CAS 0–0–ns9
t
RRH
Read command hold time to RAS 0–0–ns9
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Write cycle
Read-modify-write cycle
Refresh cycle
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
WCS
Write command setup time 0 – 0 – ns 11
t
WCH
Write command hold time 10 – 10 – ns 11
t
WP
Write command pulse width 10 – 10 – ns
t
RW L
Write command to RAS lead time 10 – 10 – ns
t
CWL
Write command to CAS lead time 8 – 10 – ns
t
DS
Data-in setup time 0 – 0 – ns 12
t
DH
Data-in hold time 8 – 10 – ns 12
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
RW C
Read-write cycle time 113 – 135 – ns
t
RW D
RAS to WE delay time 67 – 77 – ns 11
t
CWD
CAS to WE delay time 32 – 35 – ns 11
t
AW D
Column address to WE delay time 42 – 47 – ns 11
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
CSR
CAS setup time (CAS-before-RAS)5 – 5 – ns3
t
CHR
CAS hold time (CAS-before-RAS)8 – 10 – ns3
t
RPC
RAS precharge to CAS hold time 0 – 0 – ns
t
CPT
CAS
precharge time
(CBR counter test)
10 10 – ns
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P. 8 of 16
Hyper page mode cycle
Output enable
Self-refresh cycle
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
CPWD
CAS precharge to WE delay time 45 – 52 – ns
t
CPA
Access time from CAS precharge – 28 – 35 ns 13
t
RASP
RAS pulse width 50 100K 60 100K ns
t
DOH
Previous data hold time from CAS 5–5–ns
t
REZ
Output buffer turn off delay from RAS 0 13 0 15 ns
t
WEZ
Output buffer turn off delay from WE 0 13 0 15 ns
t
OEZ
Output buffer turn off delay from OE 0 13 0 15 ns
t
HPC
Hyper page mode cycle time 20 – 25 – ns
t
HPRWC
Hyper page mode RMW cycle 47 – 56 – ns
t
RHCP
RAS hold time from CAS 30 – 35 – ns
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
CLZ
CAS to output in Low Z 0 – 0 – ns 8
t
ROH
RAS hold time referenced to OE 8–10–ns
t
OEA
OE access time – 13 – 15 ns
t
OED
OE to data delay 13 – 15 – ns
t
OEZ
Output buffer turnoff delay from OE 0 13 0 15 ns 8
t
OEH
OE command hold time 10 – 10 – ns
t
OLZ
OE to output in Low Z 0 – 0 – ns
t
OFF
Output buffer turn-off time 0 13 0 15 ns 8,10
Std
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
RASS
RAS pulse width
(CBR self refresh)
100 – 100 – µs
t
RPS
RAS precharge time
(CBR self refresh)
90 – 105 – ns
t
CHS
CAS
hold time
(CBR self refresh)
-50 – -50 – ns
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Notes
1I
CC1
, I
CC3
, I
CC4
, and I
CC6
are dependent on frequency.
2I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
3 An initial pause of 200 µs is required after power-up followed by any 8 RAS
cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS
-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4 AC Characteristics assume t
T
= 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL(min) ≥ GND and VIH
(max)
≤ V
CC
.
5V
IH
(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
6 Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point only. If t
RCD
is greater than the
specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
7 Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point only. If t
RAD
is greater than the
specified t
RAD
(max) limit, then access time is controlled exclusively by tAA.
8 Assumes three state test load (5 pF and a 380
Ω
Thevenin equivalent).
9Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10 t
OFF
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
OFF
is referenced from
rising edge of RAS
or CAS, whichever occurs last.
11 t
WCS
, t
WCH
, t
RW D
, t
CWD
and t
AW D
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If t
WS
≥ t
WS
(min) and t
WH
≥ t
WH
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
cycle. If t
RW D
≥ t
RW D
(min), t
CWD
≥ t
CWD
(min) and t
AWD
≥ t
AW D
(min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS
leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t
CAA
or t
CAC
or t
CPA
14 t
ASC
≥ t
CP
to achieve tPC (min) and t
CPA
(max) values.
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C4M4EOQ 5V devices.
17 These characteristics apply to AS4C4M4E1Q 5V devices.
AC test conditions
Key to switching waveforms
- Access times are measured with output reference levels of VOH =
2.4V and V
OL
= 0.4V,
V
IH
= 2.4V and VIL = 0.8V
- Input rise and fall times: 2 ns
100 pF*
R2 = 295
Ω
R1 = 828
Ω
D
out
GND
+5V
Figure A: Equivalent output load
*including scope
and jig capacitance
*including scope
and jig capacitance
50 pF*
R2 = 295
Ω
R1 = 828
Ω
D
out
GND
+3.3V
Figure B: Equivalent output load
(AS4C4M4E0/AS4C4M4E1)(AS4C4M4E0/AS4C4M4E1)
Undefined output/don’t careFalling inputRising input
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Read waveform
Early write waveform
t
RAS
t
RC
t
RP
t
RSH
t
RAD
t
RCH
t
ROH
t
CAC
t
OEA
t
OFF
(see note 11)
t
OEZ
RAS
CAS
Address
WE
OE
DQ
Column address
t
CRP
t
CSH
t
RCD
t
ASC
t
CAH
t
CAS
t
RAL
t
RAH
t
RCS
t
AA
t
CLZ
t
RRH
Data out
t
RAC
t
ASR
Row address
t
ROH
t
WEZ
t
OLZ
t
REZ
t
RAS
t
RC
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
RAD
t
ASC
t
CAH
t
WCS
t
CWL
t
RW L
t
WCH
t
WP
t
DS
t
DH
Data in
RAS
CAS
Address
WE
OE
DQ
Row address
t
RAL
Column address
t
RAH
t
ASR
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Write waveform
OE controlled
Read-modify-write waveform
Row address
t
RAS
t
RC
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
RAH
t
RAL
t
RAD
t
CAH
t
CWL
t
RWL
t
OEH
t
DS
t
DH
Data in
RAS
CAS
Address
WE
OE
DQ
Column address
t
WP
t
ASC
t
ASR
t
OED
t
RAS
t
RW C
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
RAD
t
RAL
t
AR
t
CAH
t
CWL
t
CWD
t
RW L
t
AW D
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
DS
t
DH
Row address Column address
Data inData out
RAS
CAS
Address
WE
OE
DQ
t
RAH
t
RWD
t
RCS
t
RAC
t
OEZ
t
OED
t
ASC
t
ASR
t
OLZ
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EDO page mode read waveform
EDO page mode early write waveform
Row
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
t
CSH
t
RSH
t
HPC
t
ASR
t
RAD
t
RRH
t
OEA
t
OEA
t
AA
t
RAC
t
CAC
t
OEZ
Data out
Data out
Data out
Col address
Col address
RAS
CAS
Address
WE
OE
DQ
t
AR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
CLZ
t
CP
t
OFF
t
OEZ
Col address
t
RCH
t
CPA
t
RHCP
t
CLZ
t
CLZ
t
OLZ
t
CPA
t
RAH
t
RASP
t
RW L
t
ASC
t
WCS
t
CP
t
RAL
t
WCH
t
CWL
t
WP
t
DS
t
DH
t
OED
t
CAS
Col address
Col address Col address
Data in Data In Data in
RAS
CAS
Address
WE
OE
DQ
t
PC
t
CAH
t
CSH
t
RCD
t
OEH
t
HDR
t
AR
t
RAD
t
ASR
t
CRP
t
RSH
Row address
Page 13
®
AS4C4M4EOQ
AS4C4M4E1Q
3/22/01; v.1.0
Alliance Semiconductor
P. 13 of 16
EDO page mode read-modify-write waveform
CAS before RAS refresh waveform
WE = A = VIH or V
IL
RAS only refresh waveform
WE = OE = VIH or V
IL
t
RASP
t
RP
t
RCD
t
CSH
t
CAS
t
CP
t
CRP
t
ASR
t
CAH
t
CAH
t
RAL
t
CAH
t
CWD
t
AWD
t
CWD
t
CWL
t
CWD
t
AWD
t
RW L
t
WP
t
OEZ
t
OEA
t
RAC
t
DS
t
CLZ
t
CAC
t
CPA
Row ad Col ad Col addressCol ad
Data out
Data inData in
Data outData out
Data in
RAS
CAS
Address
WE
OE
DQ
t
RAD
t
RAH
t
RWD
t
RCS
t
CWL
t
OEA
t
AA
t
DH
t
DS
t
CLZ
t
CAC
t
CLZ
t
CAC
t
OED
t
HPRWC
t
CPWD
t
ASC
t
ASC
t
ASC
t
RP
t
RC
t
RAS
t
RPC
t
CP
t
CSR
t
CHR
RAS
CAS
DQ
OPEN
t
RAS
t
RP
t
RC
t
CRP
t
RPC
t
ASR
t
RAH
Row address
RAS
Address
CAS
Page 14
AS4C4M4EOQ
AS4C4M4E1Q
®
3/22/01; v.1.0
Alliance Semiconductor
P. 14 of 16
Hidden refresh waveform (read)
Hidden refresh waveform (write)
t
RAS
t
RC
t
RP
t
RAS
t
RC
t
RP
t
CRP
t
RCD
t
RSH
t
CRP
t
CHR
t
ASR
t
RAD
t
ASC
t
RRH
t
OEA
t
CLZ
t
CAC
t
OEZ
Col addressRow
Data out
RAS
CAS
Address
WE
OE
DQ
t
AR
t
RAH
t
RAC
t
AA
t
RCS
t
CAH
t
OFF
t
RAS
t
RC
t
RP
t
CRP
t
RCD
t
RSH
t
ASR
t
RAH
t
RAD
t
AR
t
CAH
t
WCS
t
WCH
t
DS
t
DH
Data in
Col addressRow address
RAS
CAS
Address
WE
DQ
OE
t
ASC
t
RWL
t
WCR
t
WP
t
DHR
t
RAL
t
CHR
Page 15
®
AS4C4M4EOQ
AS4C4M4E1Q
3/22/01; v.1.0
Alliance Semiconductor
P. 15 of 16
CAS before RAS refresh counter test waveform
t
RAS
t
RSH
t
RP
t
CSR
t
CHR
t
CPT
t
CAS
t
CAH
t
CLZ
t
CAC
t
RCH
t
RRH
t
ROH
t
OEA
t
RWL
t
CWL
t
WCS
t
WP
t
WCH
t
DS
t
DH
t
RCS
t
OEA
t
DS
t
DH
Col address
Data out
Data in
Data out Data in
RAS
CAS
Address
DQ
WE
OE
WE
DQ
OE
WE
OE
DQ
t
OED
t
AA
t
CLZ
t
CAC
t
OEZ
t
WP
t
CWL
t
RCS
t
AA
t
OEZ
t
AWD
t
CWD
t
RAL
Read cycleWrite cycleRead-Write cycle
t
ASC
t
OFF
t
RWL
Page 16
AS4C4M4EOQ
AS4C4M4E1Q
®
3/22/01; v.1.0
Alliance Semiconductor
P. 16 of 16
CAS-before-RAS self refresh cycle
Capacitance
15
ƒ = 1 MHz, Ta = Room temperature
4C4M4EOQ ordering information
AS4C4M4E1Q ordering information
4C4M4EOQ family part numbering system
Parameter Symbol Signals Test conditions Max Unit
Input capacitance
C
IN1
A0 to A9 Vin = 0V 5 pF
C
IN2
RAS, UCAS, LCAS, WE, OE Vin = 0V 7 pF
DQ capacitance C
DQ
DQ0 to DQ15 Vin = V
out
= 0V 7 pF
Package \ RAS access time 50 ns 60 ns
Plastic SOJ, 300 mil, 24/26-pin 5V 4C4M4EOQ-50JC 4C4M4EOQ-60JC
Plastic TSOP, 300 mil, 24/26-pin 5V 4C4M4EOQ-50TC 4C4M4EOQ-60TC
Package \ RAS
access time 50 ns 60 ns
Plastic SOJ, 300 mil, 24/26-pin 5V AS4C4M4E1Q-50JC AS4C4M4E1Q-60JC
Plastic TSOP, 300 mil, 24/26-pin 5V AS4C4M4E1Q-50TC AS4C4M4E1Q-60TC
AS4 C 4M4 E0 –XX X C
DRAM
prefix
C = 5V CMOS
LC = 3.3V CMOS
4M×4
E0=4K refresh
E1=2K refresh
RAS
access
time
Package:
J = SOJ 300 mil, 24/26
T = TSOP 300 mil, 24/26
Commercial temperature
range, 0°C to 70 °C
t
RP
t
RASS
t
RPC
t
CP
t
CHS
t
CEZ
RAS
UCAS,
DQ
LCAS
t
RPS
t
CSR
t
RPC
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