Datasheet 4017 Datasheet

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Page 1

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4017B MSI

5-stage Johnson counter

Product speciﬁcation File under Integrated Circuits, IC04

January 1995

Page 2

Philips Semiconductors Product speciﬁcation

5-stage Johnson counter

DESCRIPTION

The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Ooto O9), an active LOW output from the most significant flip-flop (O active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR).

The counter is advanced by either a LOW to HIGH transition at CP0while CP1is LOW or a HIGH to LOW transition at CP1while CP0is HIGH (see also function table).

When cascading counters, the

output, which is LOW

5-9

while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0input of the next counter.

5-9

HEF4017B

A HIGH on MR resets the counter to zero

= O

clock inputs (CP0, CP1). Automatic code correction of the counter is provided by an

internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

= HIGH; O1to O9= LOW) independent of the

5-9

MSI

Fig.1 Functional diagram.

Fig.2 Pinning diagram.

HEF4017BP(N): 16-lead DIL; plastic (SOT38-1) HEF4017BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4017BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America

January 1995 2

PINNING

CP CP

0 1

clock input (LOW to HIGH triggered)

clock input (HIGH to LOW triggered) MR master reset input O

to O

5-9

FAMILY DATA, I

decoded outputs

carry output (active LOW)

LIMITS category MSI

See Family Specifications

Page 3

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January 1995 3

Philips Semiconductors Product speciﬁcation

5-stage Johnson counter

Fig.3 Logic diagram.

HEF4017B

MSI

Page 4

Philips Semiconductors Product speciﬁcation

5-stage Johnson counter

FUNCTION TABLE

MR CP

HXXO

L H Counter advances

L L Counter advances L L X No change

L X H No change L H No change

L L No change

AC CHARACTERISTICS

= 0 V; T

amb

Propagation delays

CP0, CP1→ O0to O

HIGH to LOW 10 t

LOW to HIGH 10 t

CP0, CP1→ O

HIGH to LOW 10 t

LOW to HIGH 10 t

MR → O1to O

HIGH to LOW 10 t

MR → O

5-9

LOW to HIGH 10 t

MR → O

LOW to HIGH 10 t

OPERATION

5-9

=25°C; CL= 50 pF; input transition times ≤ 20 ns

5 140 280 ns 113 ns + (0,55 ns/pF) C

15 40 80 ns 32 ns + (0,16 ns/pF) C

5 125 250 ns 98 ns + (0,55 ns/pF) C

15 40 80 ns 32 ns + (0,16 ns/pF) C

5-9

5 145 290 ns 118 ns + (0,55 ns/pF) C

15 40 80 ns 32 ns + (0,16 ns/pF) C

5 125 250 ns 98 ns + (0,55 ns/pF) C

15 40 80 ns 32 ns + (0,16 ns/pF) C

5 115 230 ns 88 ns + (0,55 ns/pF) C

15 35 70 ns 27 ns + (0,16 ns/pF) C

5 110 220 ns 83 ns + (0,55 ns/pF) C

15 35 70 ns 27 ns + (0,16 ns/pF) C

5 130 260 ns 103 ns + (0,55 ns/pF) C

15 40 75 ns 32 ns + (0,16 ns/pF) C

Notes

1. H = HIGH state (the more positive voltage)

= H; O1to O9=L

2. L = LOW state (the less positive voltage)

3. X = state is immaterial

4. = positive-going transition

5. = negative-going transition

SYMBOL MIN. TYP. MAX.

PHL

PLH

PHL

PLH

PHL

PLH

55 110 ns 44 ns + (0,23 ns/pF) C

50 100 ns 39 ns + (0,23 ns/pF) C

55 110 ns 44 ns + (0,23 ns/pF) C

50 100 ns 39 ns + (0,23 ns/pF) C

45 90 ns 34 ns + (0,23 ns/pF) C

55 105 ns 44 ns + (0,23 ns/pF) C

HEF4017B

MSI

TYPICAL EXTRAPOLA TION

FORMULA

L L L L L L L L L L L L L L L L L L L L L

January 1995 4

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Philips Semiconductors Product speciﬁcation

5-stage Johnson counter

SYMBOL MIN. TYP. MAX.

Output transition

times 5 60 120 ns 10 ns + (1,0 ns/pF) C HIGH to LOW 10 t

THL

30 60 ns 9 ns + (0,42 ns/pF) C

15 20 40 ns 6 ns + (0,28 ns/pF) C

5 60 120 ns 10 ns + (1,0 ns/pF) C

LOW to HIGH 10 t

TLH

30 60 ns 9 ns + (0,42 ns/pF) C

15 20 40 ns 6 ns + (0,28 ns/pF) C

AC CHARACTERISTICS

= 0 V; T

=25°C; CL= 50 pF; input transition times ≤ 20 ns

amb

SYMBOL MIN. TYP. MAX.

Hold times 5 90 45 ns

→CP

10 t

hold

40 20 ns

15 20 10 ns

58040ns

CP1→ CP

10 t

hold

40 20 ns

15 30 10 ns

Minimum clock

pulse width: 5

= LOW; 10 40 20 ns see also waveforms

CP1= HIGH 15 30 15 ns Figs 4 and 5

WCPL

WCPH

80 40 ns

Minimum MR 5 50 25 ns

pulse width; HIGH 10 t

WMRH

30 15 ns

15 20 10 ns

Recovery time 5 60 30 ns

for MR 10 t

RMR

30 15 ns

15 20 10 ns

Maximum clock 5 6 12 MHz

pulse frequency 10 f

max

12 24 MHz

15 15 30 MHz

TYPICAL EXTRAPOLA TION

HEF4017B

MSI

FORMULA

L L

Dynamic power 5 500 f

dissipation per 10 2200 f package (P) 15 6000 f

TYPICAL FORMULA FOR P (µW)

+∑(foCL) × V

January 1995 5

DD DD DD

2 2 2

where fi= input freq. (MHz) fo= output freq. (MHz) C

= load cap. (pF)

∑ (f

) = sum of outputs

oCL

= supply voltage (V)

Page 6

Philips Semiconductors Product speciﬁcation

5-stage Johnson counter

HEF4017B

MSI

Fig.4 Waveforms showing hold times for CP0to CP1and CP1to CP0. Hold times are shown as positive values,

but may be specified as negative values.

Conditions: CP1= LOW while CP0is triggered on a LOW to HIGH transition. t

also apply when CP0= HIGH and CP1is triggered on a HIGH to LOW transition.

RMR

Fig.5 Waveforms showing recovery time for MR; minimum CP0and MR pulse widths.

January 1995 6

WCP

and

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Philips Semiconductors Product speciﬁcation

5-stage Johnson counter

HEF4017B

MSI

Fig.6 Timing diagram.

January 1995 7

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Philips Semiconductors Product speciﬁcation

5-stage Johnson counter

HEF4017B

MSI

APPLICATION INFORMATION

Some examples of applications for the HEF4017B are:

• Decade counter with decimal decoding

• 1 out of n decoding counter (when cascaded)

• Sequential controller

• Timer.

Figure 7 shows a technique for extending the number of decoded output states for the HEF4017B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).

Fig.7 Counter expansion.

Note It is essential not to enable the counter on

an extra count.

January 1995 8

CP1when CP0is HIGH, or on CP0when CP1is LOW, as the this would cause